ELEC 7770 Advanced VLSI Design Spring 2008 VLSI Yield and Moore’s LawVLSI Chip YieldImportance of YieldClustered VLSI DefectsYield ParametersYield EquationEffect of Defect ClusteringRanges of Yield ParametersReferencesGordon E. Moore1965Moore’s 1965 Graph1975Figure 5 of Moore’s 1975 Paper1995Also in the 1995 PaperMoore’s Law2008Spring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2008Spring 2008VLSI Yield and Moore’s LawVLSI Yield and Moore’s LawVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlSpring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22VLSI Chip YieldVLSI Chip YieldVLSI Chip YieldVLSI Chip YieldA manufacturing defect is a finite chip area with A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by electrically malfunctioning circuitry caused by errors in the fabrication process.errors in the fabrication process.A chip with no manufacturing defect is called a A chip with no manufacturing defect is called a good chip.good chip.Fraction (or percentage) of good chips produced Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. in a manufacturing process is called the yield. Yield is denoted by symbol Yield is denoted by symbol YY..Spring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Importance of YieldImportance of YieldCost of a chip =Cost of a chip =Cost of fabricating and testing a waferYield × Number of chip sites on the waferSpring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Clustered VLSI DefectsClustered VLSI DefectsClustered VLSI DefectsClustered VLSI DefectsWaferDefectsFaulty chipsGood chipsUnclustered defectsWafer yield = 12/22 = 0.55Clustered defects (VLSI)Wafer yield = 17/22 = 0.77Spring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Yield ParametersYield ParametersYield ParametersYield ParametersDefect density (Defect density (d d ) = Average number of defects per unit ) = Average number of defects per unit chip areachip areaChip area (Chip area (A A ))Clustering parameter (Clustering parameter ())Negative binomial distribution of defects, Negative binomial distribution of defects, p p ((x x ) = Prob(number of defects on a chip = ) = Prob(number of defects on a chip = x x )) Γ (α +x ) (Ad / α) x=  .  x ! Γ (α) (1+Ad / α) α+xwhere Γ is the gamma functionα = 0, p (x ) is a delta function (max. clustering)α =  , p (x ) is Poisson distribution (no clustering)Spring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Yield EquationYield EquationYield EquationYield EquationY = Prob( zero defect on a chip ) = p (0)Y = ( 1 + Ad / α ) – α Example: Ad = 1.0, α = 0.5, Y = 0.58Unclustered defects: α = , Y = e – AdExample: Ad = 1.0, α = , Y = 0.37too pessimistic !Spring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Effect of Defect ClusteringEffect of Defect Clustering0 0.5 1.0 1.5 2.01.000.750.500.250.00YieldAd = 0.5Clustering Parameter, αe-0.5 = 0.607Spring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Ranges of Yield ParametersRanges of Yield ParametersYield of1 cm2 chipDefect density, d in defects per cm20.1 1.55.00.50.9130.9060.500.27Clustering parameter, αMature processInitial processSpring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99ReferencesReferencesClustered yield modelClustered yield modelM. L. Bushnell and V. D. Agrawal, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI CircuitsDigital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, , Springer, 2000, Chapter 3.Chapter 3.C. H. Stapper, “On Yield, Fault Distributions, and Clustering of C. H. Stapper, “On Yield, Fault Distributions, and Clustering of Particles,” Particles,” IBM Jour. of Res. and DevIBM Jour. of Res. and Dev., vol. 30, no. 3, pp. 326-338, ., vol. 30, no. 3, pp. 326-338, May 1986.May 1986.The unclustered defect model was first described in paper:The unclustered defect model was first described in paper:B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,” B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,” Proc. IEEEProc. IEEE, vol. 52, no. 12, pp. 1537-1545, December 1964., vol. 52, no. 12, pp. 1537-1545, December 1964.A general reference on clustered distributions:A general reference on clustered distributions:A. Rogers, A. Rogers, Statistical Analysis of Spatial DispersionsStatistical Analysis of Spatial Dispersions, London, United , London, United Kingdom: Pion Limited, 1974.Kingdom: Pion Limited, 1974.Spring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010Gordon E. MooreGordon E. MooreSpring 08, Jan 17Spring 08, Jan 17ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)111119651965““Cramming More Components onto Integrated Cramming More Components onto Integrated Circuits,” Circuits,” ElectronicsElectronics, vol. 38, no. 8, April 19, 1965., vol. 38, no. 8, April 19, 1965.The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to