ELEC 7770 Advanced VLSI Design Spring 2008 Fault SimulationFault SimulationProblem and MotivationFault Simulator in VLSI DesignFault Simulation ScenarioFault Simulation Scenario (Cont.)Fault Simulation AlgorithmsSerial AlgorithmSerial Algorithm (Cont.)Parallel Fault SimulationParallel Fault Simulation ExampleDeductive Fault SimulationDeductive Fault Sim. ExampleConcurrent Fault SimulationConcurrent Fault Sim. ExampleFault SamplingMotivation for SamplingRandom Sampling ModelProbability Density of Sample Coverage, cSampling Error BoundsSummaryExerciseExercise AnswerSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2008Spring 2008Fault SimulationFault SimulationVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22Fault SimulationFault SimulationProblem and motivationFault simulation algorithmsSerialParallelDeductiveConcurrentRandom Fault SamplingSummaryReview problemsSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Problem and MotivationProblem and MotivationFault simulation Problem:GivenA circuitA sequence of test vectorsA fault modelDetermineFault coverage - fraction (or percentage) of modeled faults detected by test vectorsSet of undetected faultsMotivationDetermine test quality and in turn product qualityFind undetected fault targets to improve testsSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Fault Simulator in VLSI DesignFault Simulator in VLSI DesignVerified designnetlistVerificationinput stimuliFault simulator Test vectorsModeledfault listTestgeneratorTestcompactorFaultcoverage?Remove tested faultsDeletevectorsAdd vectorsLowAdequateStopSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Fault Simulation ScenarioFault Simulation ScenarioCircuit model: mixed-levelMostly logic with some switch-level for high-impedance (Z) and bidirectional signalsHigh-level models (memory, etc.) with pin faultsSignal states: logicTwo (0, 1) or three (0, 1, X) states for purely Boolean logic circuitsFour states (0, 1, X, Z) for sequential MOS circuitsTiming:Zero-delay for combinational and synchronous circuitsMostly unit-delay for circuits with feedbackSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Fault Simulation Scenario (Cont.)Fault Simulation Scenario (Cont.)Faults:Mostly single stuck-at faultsSometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common useEquivalence fault collapsing of single stuck-at faultsFault-dropping – a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosisFault sampling – a random sample of faults is simulated when the circuit is largeSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Fault Simulation AlgorithmsFault Simulation AlgorithmsSerialSerialParallelParallelDeductiveDeductiveConcurrentConcurrentDifferential*Differential** See M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 5.Spring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Serial AlgorithmSerial AlgorithmAlgorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:Modify netlist by injecting one faultSimulate modified netlist, vector by vector, comparing responses with saved responsesIf response differs, report fault detection and suspend simulation of remaining vectorsAdvantages:Easy to implement; needs only a true-value simulator, less memoryMost faults, including analog faults, can be simulatedSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99Serial Algorithm (Cont.)Serial Algorithm (Cont.)Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuitsAlternative: Simulate many faults togetherTest vectors Fault-free circuit Circuit with fault f1Circuit with fault f2Circuit with fault fnComparatorf1 detected?Comparatorf2 detected?Comparatorfn detected?Spring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010Parallel Fault SimulationParallel Fault SimulationCompiled-code method; best with two-states (0,1)Exploits inherent bit-parallelism of logic operations on computer wordsStorage: one word per line for two-state simulationMulti-pass simulation: Each pass simulates w-1 new faults, where w is the machine word lengthSpeed up over serial method ~ w-1Not suitable for circuits with timing-critical and non-Boolean logicSpring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1111Parallel Fault Simulation ExampleParallel Fault Simulation Examplea b c d e f g 1 1 11 1 11 0 11 0 10 0 01 0 1s-a-1s-a-00 0 1c s-a-0 detectedBit 0: fault-free circuitBit 1: circuit with c s-a-0Bit 2: circuit with f s-a-1Spring 08, Mar 27Spring 08, Mar 27ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1212Deductive Fault SimulationDeductive Fault SimulationOne-pass simulationEach line k contains a list Lk of faults detectable on it Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault listsPO fault lists provide detection dataLimitations:Set-theoretic rules