ELEC 7770 Advanced VLSI Design Spring 2007 Zero-Skew DesignZero-Skew Clock RoutingZero-Skew: ReferencesZero-Skew RoutingBalancing Subtrees (1)Balancing Subtrees (2)Balancing Subtrees (3)Balancing Subtrees Example 1Example 1Balancing Subtrees, x > 1Balancing Subtrees Example 2Example 2, x = 1.0225Example 2, L = 1.255mmBalancing Subtrees, x < 1Balancing Subtrees Example 3Example 3, x = – 0.0225Example 3, L = 1.255mmZero-Skew DesignNonzero-Skew DesignConclusionSpring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2007Spring 2007ZeroZero--Skew DesignSkew DesignVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07Spring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22Zero-Skew Clock RoutingZero-Skew Clock RoutingFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFCKSpring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Zero-Skew: ReferencesZero-Skew: ReferencesH-TreeH-TreeA. L. Fisher and H. T. Kung, “Synchronizing Large A. L. Fisher and H. T. Kung, “Synchronizing Large Systolic Arrays,” Systolic Arrays,” Proc. SPIEProc. SPIE, vol. 341, pp. 44-52, , vol. 341, pp. 44-52, May 1982.May 1982.A. Kahng, J. Cong and G. Robins, “Hig-A. Kahng, J. Cong and G. Robins, “Hig-Performance Clock Routing Based on Recursive Performance Clock Routing Based on Recursive Geomrtric Matching,” Geomrtric Matching,” Proc. Design Automation Proc. Design Automation ConfConf., June 1991, pp. 322-327.., June 1991, pp. 322-327.M. A. B. Jackson, A. Srinivasan and E. S. Kuh, M. A. B. Jackson, A. Srinivasan and E. S. Kuh, “Clock Routing for High-Performance IC’s,” “Clock Routing for High-Performance IC’s,” Proc. Proc. Design Automation ConfDesign Automation Conf., June 1990, pp. 573-579.., June 1990, pp. 573-579.Spring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Zero-Skew RoutingZero-Skew RoutingBuild clock tree bottom up:Build clock tree bottom up:Leaf nodes are all equal loading flip-flops.Leaf nodes are all equal loading flip-flops.Two zero-skew subtrees are joined to form a larger zero-skew Two zero-skew subtrees are joined to form a larger zero-skew subtree.subtree.Entire clock tree is built recursively.Entire clock tree is built recursively.R.-S. Tsay, “An Exact Zero-Skew Clock Routing R.-S. Tsay, “An Exact Zero-Skew Clock Routing Algorithm,” Algorithm,” IEEE Trans. CADIEEE Trans. CAD, vol. 12, no. 2, pp. 242-, vol. 12, no. 2, pp. 242-249, Feb. 1993.249, Feb. 1993.J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal J. Rubenstein, P. Penfield and M. A. Horowitz, “Signal Delay in RC Tree Networks,” Delay in RC Tree Networks,” IEEE Trans. CADIEEE Trans. CAD, vol. 2, , vol. 2, no. 3, pp. 202-211, July 1983.no. 3, pp. 202-211, July 1983.Spring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Balancing Subtrees (1)Balancing Subtrees (1)t1C1c1/2c1/2t2C2c2/2c2/2r1r2(1 – x)LxLTapping pointSubtree 1Subtree 2ABSpring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Balancing Subtrees (2)Balancing Subtrees (2)Subtrees 1 and 2 are each balanced (zero-skew) Subtrees 1 and 2 are each balanced (zero-skew) trees, with delays t1 and t2 to respective leaf trees, with delays t1 and t2 to respective leaf nodes.nodes.Total capacitances of subtrees are C1 and C2, Total capacitances of subtrees are C1 and C2, respectively.respectively.Connect points A and B by a minimum-length Connect points A and B by a minimum-length wire of length L.wire of length L.Determine a tapping point x such that wire Determine a tapping point x such that wire lengths xL and (1 – x)L produce zero skew.lengths xL and (1 – x)L produce zero skew.Spring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Balancing Subtrees (3)Balancing Subtrees (3)Use Elmore delay formula:Use Elmore delay formula:r1(C1 + c1/2) + t1 = r2(C2 + c2/2) + t2r1(C1 + c1/2) + t1 = r2(C2 + c2/2) + t2Substitute:Substitute:r1 = axL, r2 = a(1 – x)Lr1 = axL, r2 = a(1 – x)Lc1 = bxL, c2 = b(1 –x)Lc1 = bxL, c2 = b(1 –x)LabL2x + (C1+C2)x = (t2 – t1) + aL(C2+bL/2)abL2x + (C1+C2)x = (t2 – t1) + aL(C2+bL/2)Then solve for x:Then solve for x:(t2 – t1) + aL (C2 + bL/2)(t2 – t1) + aL (C2 + bL/2)x =x =──────────────────────────────── aL(bL + C1 + C2)aL(bL + C1 + C2)Spring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Balancing Subtrees Example 1Balancing Subtrees Example 1Subtree parameters:Subtree parameters:Subtree 1: t1 = 5ps, C1 = 3pFSubtree 1: t1 = 5ps, C1 = 3pFSubtree 2: t2 = 10ps, C2 = 6pFSubtree 2: t2 = 10ps, C2 = 6pFInterconnect:Interconnect:L = 1mmL = 1mmWire parameters: a = 100Wire parameters: a = 100ΩΩ/cm, b = 1pF/cm/cm, b = 1pF/cmTapping point:Tapping point:(t2 – t1) + aL (C2 + bL/2)(t2 – t1) + aL (C2 + bL/2)(10–5) + 100(10–5) + 100×0.1(6 + 1×0.1/2)×0.1(6 + 1×0.1/2)x =x =──────────────── =──────────────── = ────────────────── ────────────────── aL (bL + C1 + C2)aL (bL + C1 + C2) 100×0.1(1×0.1+3+6) 100×0.1(1×0.1+3+6) = (5 + 60.5)/(10= (5 + 60.5)/(10×9.1) = 0.7198×9.1) = 0.7198Spring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99Example 1Example 1FFFFFFFFFFFFFFTo next levelSubtree 1Subtree 20.7198mm0.2802mmSpring 07, Apr 3Spring 07, Apr 3ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010Balancing Subtrees, x > 1Balancing Subtrees, x > 1Tapping point set at root of tree with larger