Physical Design: Layout in Automated IC Design -Kyungseok KimFollowing ASIC design flow (Fig.1.), front-end design consists of creating the logic for the design,simulation, and test vector generation. The logic could be automatically generated by the synthesis step,which generates gate-level netlists, with hardware description language (VHDL, Verilog). Also, It isdirectly designed by schematic drawing as a manual source. After having a logic source, we could usesimulators and test vector generators to test the design in the gate-level. For layout, there are two typesof layout procedures. One is creating an IC layout from schematics or a netlist by placing standard cellsinto a layout and performing automatic routing between the blocks or cells in the automated IC design.The other is manually creating and editing each polygon by the layout editors in full custom IC design.For this design project, the layout of design will be automatically generated by placing the standardcells from a gate level netlist following the automated IC design scheme. The layout stage (Fig.2.)consists of several steps to present the design in physical device level masks under design rules whichdepends on each technology vendor for fabricating a real chip. In first step, library creation is theprocess of creating a library of standard cells that are used in the design. A cell library is a design objectwhich contains the cells in the design. Floorplanning is the process of estimating the chip area that willbe used for each standard cell or block. A floorplan is a topological structure comprised of rows andshapes used as guides for placing cells in the design. Placement is the process of placing standardcellsor blocks onto the floorplan. Then, the process of placing and connecting signal and power pathsbetween the standard cells or blocks is done the in routing stage. After routing, compaction is executedto minimize the size of a completed layout. Finally, we need to determine whether the layout conformsto the design rules, corresponds to the source schematic, and performs satisfactorily. Then, the masklayout is transferred to patterns that can be used to generate a real IC in the stage of design verificationand pattern generation. <Fig.1.> ASIC Design Flow in Dr. Nelson’s lecture note <Fig.2.> Automated Layout Design FlowLayout Procedure: There are two designs to demonstrate the layout stage flowing automated ICdesign flow in TSMC 0.18um technology. The layout for the design project of CPU is not completewith overwhelming overflows after routing step. So, alternative design (MUX) gives the example ofwhole layout procedure with extract parameters, lumped R and C. Design project for CPU -Schematic design with a symbol from logic source came from the synthesis step: The gate level netlist of CPU can be existed as one Verilog file and handed over the layout procedure.At that time, we could layout only flat option. Then, it makes the complexity of routing and generatestoo many overflows which couldn’t automatically route the signal nets between the cells. We need todraw the signal nets manually to complete the layout procedure. The suggestion is that the design insynthesis step would be separated and blocked into each functional component for reducing thecomplexity of routing and managing the overflows. Scan-test component is added to design by DFT tools.<Source: CPU_areaOPt_scan.v>- Floorplanning: Before placing stardard-cells, Floorplan automatically generated by the tools and we could also specifythe area and the internal inventories such as rows, channel, and aspect ration. The specifications ofautomatically generate floorplan are tabulated in the following:Total area 157284512 um2# of internal rows 55Avg. instance height 120.0 umAvg. channel height 120.0 umTotal connections(pins-nets) 44099Internal zone width 12008.0 umInternal zone height 13204.0 umAspect ratio 0.93<Floorplan>- Placement for Std. Cells:Each technology package provides its own standard cells in the library. This stage places all cells whichare used in the design on the floorplan. Then, all cells are connected by signal nets and ports beforerouting. < Entire Design Cells > <Zoom-In> < Connect Ports >- Automated routing:For routing, there are several routing options to reduce the wire-length, the congestion of signal nets,and the overflows. For our CPU design, there are so many overflows more than 6678 after routingprocedure. It could be caused to choose the flat scheme instead of the hierarchical scheme for thedesign. Also, the overflows depend on the algorithm of routing. Unfortunately, the layout for CPUcouldn’t be completed by overflows. The considerable size of designs would be implemented by blockshierarchically. For the benefit of hierarchical design in large circuits, a designer could manuallyhandled more on existed problems for the correct route. Number of Overflows: 6678Number of Global routing nodes: 157444Number of Global routing arcs: 201136Check Shorts: O.K.Overflows Changing Options In Auto RouteAlternative Design for demonstrating whole layout procedure: MUX The verified Mux design is personally chosen to show a layout procedure without verification offunctionality, because it is already proved by a VHDL code provider.1. VHDL codes are presented in Appendix I2. Gate level netlist are generated by the Mentor DA-IC tools in Appendix II3. Completed layout from the Mentor IC StationTotal area = 94848.0 um2 Number of core instances = 12Number of signal nets = 26 Number of power nets = 2Number of global routing nodes = 156 Number of global routing arcs = 167Avg. instance height = 120.0 um Avg. channel height = 32.0 umAspect ratio = 1.73 DRC & LVS Check: O.K.4. Extract the parameters of lumped R & C and Couped C from the Mentor Calibre in Appendix III Tip: After finishing DRC& LVS check, push Calibre in the Menu from the IC station and then, givethe path ( /opt/mentor/Calibre2005.2) in Setup for executing the Calibre correctly.Conclusion: During the layout procedure, some problems are not expected before doing the layout with a little bigcircuit. Especially, automated layout has to be related to the previous stages and strategy in ASICdesign flow. It is needed to keep good communications with logic level designers and solve theproblems using the options