ELEC 7770 Advanced VLSI Design Spring 2008 Design for Testability (DFT): ScanScan DesignScan StructureScan Design RulesCorrecting a Rule ViolationScan Flip-Flop (SFF)Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)Adding Scan StructureComb. Test VectorsCombinational Test VectorsTesting Scan RegisterMultiple Scan RegistersScan OverheadsHierarchical ScanOptimum Scan LayoutScan Area OverheadExample: Scan LayoutATPG Example: S5378Timing and PowerBoundary Scan Test LogicInstruction Register LoadingSystem View of InterconnectElementary Boundary Scan CellSerial Boundary ScanSummaryExercisesAnswersSpring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2008Spring 2008Design for Testability (DFT): ScanDesign for Testability (DFT): ScanVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.htmlSpring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22Scan DesignScan DesignCircuit is designed using pre-specified design rules.Circuit is designed using pre-specified design rules.Test structure (hardware) is added to the verified design:Test structure (hardware) is added to the verified design:Add a Add a test controltest control (TC) primary input. (TC) primary input.Replace flip-flops by Replace flip-flops by scan flip-flopsscan flip-flops (SFF) and connect (SFF) and connect to form one or more shift registers in the test mode.to form one or more shift registers in the test mode.Make input/output of each scan shift register Make input/output of each scan shift register controllable/observable from PI/PO.controllable/observable from PI/PO.Use combinational ATPG to obtain tests for all testable Use combinational ATPG to obtain tests for all testable faults in the combinational logic.faults in the combinational logic.Add shift register tests and convert ATPG tests into scan Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. sequences for use in manufacturing test.Spring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33Scan StructureScan StructureSFFSFFSFFCombinationallogicPIPOSCANOUTSCANINTC or TCKNot shown: CK orMCK/SCK feed allSFFs.Spring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Scan Design RulesScan Design RulesUse only clocked D-type of flip-flops for all state Use only clocked D-type of flip-flops for all state variables.variables.At least one PI pin must be available for test; At least one PI pin must be available for test; more pins, if available, can be used.more pins, if available, can be used.All clocks must be controlled from PIs.All clocks must be controlled from PIs.Clocks must not feed data inputs of flip-flops.Clocks must not feed data inputs of flip-flops.Spring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Correcting a Rule ViolationCorrecting a Rule ViolationAll clocks must be controlled from PIs.All clocks must be controlled from PIs.Comb.logicComb.logicD1D2CKQFFComb.logicD1D2CKQFFComb.logicSpring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Scan Flip-Flop (SFF)Scan Flip-Flop (SFF)DTCSDCKQQMUXD flip-flopMaster latch Slave latchCKTCNormal mode, D selectedScan mode, SD selectedMaster open Slave openttLogicoverheadSpring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Level-Sensitive Scan-Design Flip-Flop Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)(LSSD-SFF)DSDMCKQQD flip-flopMaster latch Slave latchtSCKTCKSCKMCKTCKNormalmodeMCKTCKScanmodeLogicoverheadSpring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Adding Scan StructureAdding Scan StructureSFFSFFSFFCombinationallogicPIPOSCANOUTSCANINTC or TCKNot shown: CK orMCK/SCK feed allSFFs.Spring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99Comb. Test VectorsComb. Test Vectors I2 I1O1O2S2S1N2N1CombinationallogicPIPresentstatePONextstateSCANINTCSCANOUTSpring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010Combinational Test VectorsCombinational Test Vectors I2 I1O1 O2PIPOSCANINSCANOUT S1 S2 N1 N2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0TCDon’t careor randombitsSequence length = (ncomb + 1) nsff + ncomb clock periodsncomb = number of combinational vectorsnsff = number of scan flip-flopsSpring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1111Testing Scan RegisterTesting Scan RegisterScan register must be tested prior to application of scan Scan register must be tested prior to application of scan test sequences.test sequences.A shift sequence 00110011 . . . of length A shift sequence 00110011 . . . of length nnsffsff+4+4 in scan in scan mode (TC = 0) produces 00, 01, 11 and 10 transitions in mode (TC = 0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output.all flip-flops and observes the result at SCANOUT output.Total scan test length: Total scan test length: ((nncombcomb + 2) + 2) nnsffsff + + nncombcomb + 4 + 4 clock clock periodsperiods..Example: 2,000 scan flip-flops, 500 comb. vectors, total Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 10scan test length ~ 1066 clocks. clocks.Multiple scan registers reduce test length.Multiple scan registers reduce test length.Spring 08, Apr 15Spring 08, Apr 15ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1212Multiple Scan RegistersMultiple Scan RegistersScan flip-flops can be distributed among any number Scan flip-flops can be distributed among any