04-25-2008 Mohammed Ashfaq ShukoorAdvanced VLSI Design Projecta. This example is for 4-bit unsigned integer multiplicationStateDiagram ofMultiplier Control Unitb. Design and Verification:The circuit was encoded in VHDL and was verified using a test bench.Count Step Multiplicand Product0 Initial values 0010 0000 00111 LSB=1 => Prod=Prod+Mcand 0010 0010 0011Right shift product 0010 0001 00012 LSB=1 => Prod=Prod+Mcand 0010 0011 0001Right shift product 0010 0001 10003 LSB=0 => no operation 0010 0001 1000Right shift product 0010 0000 11004 LSB=0 => no operation 0010 0000 1100Right shift product 0010 0000 0110HALTAddRShiftCheckINITStart = ’0’Start =’1’Count = 32LSB =’0’ AND Count < 32Done =’1’ Regload=’1’Mcandload = ‘1’ Shiftreg=’1’ Regload=’1’LSB =’1’ AND Count < 32Snippets of the Simulation Listing:Test ns delta Clk Reset Start Multiplier (decimal)Multiplicand(decimal)Product (decimal) Done1.Initial40 +1 1 0 1 4294967295 4294967295 0 0Final2000 +1 1 0 0 4294967295 4294967295 18446744065119617025 12.Initial2200 +1 1 0 1 1000003 10009 0 0Final3720 +1 1 0 0 1000003 10009 10009030027 13.Initial4400 +1 1 0 1 4027531843 2013275929 0 0Final6000 +1 1 0 1 4027531843 2013275929 8108532912792907147 1c. 32-bit Multiplier:Synthesized using Leonardo Spectrum with 0.35 micron tsmc technologyCircuit Statistics# of Inputs 67# of Outputs 65Critical Path Delay 12.90 nsClock Frequency 75 MHz# of combinational gates 634# of FFs 109total # of gates 1236Component Listing obtained from Leonardo:Cell Library References Total Areaand03 tsmc035_typ 1 x 2 2 gatesao32 tsmc035_typ 1 x 2 2 gatesaoi21 tsmc035_typ 4 x 1 5 gatesaoi22 tsmc035_typ 30 x 1 44 gatesaoi222 tsmc035_typ 32 x 2 72 gatesaoi32 tsmc035_typ 1 x 2 2 gatesbuf02 tsmc035_typ 5 x 1 5 gatesdff tsmc035_typ 8 x 5 38 gatesdffr tsmc035_typ 101 x 6 564 gatesinv01 tsmc035_typ 69 x 1 52 gatesinv02 tsmc035_typ 43 x 1 33 gatesmux21_ni tsmc035_typ 67 x 2 121 gatesnand02 tsmc035_typ 36 x 1 36 gatesnand03 tsmc035_typ 4 x 1 5 gatesnand04 tsmc035_typ 4 x 1 6 gatesnor02_2x tsmc035_typ 1 x 1 1 gatesnor02ii tsmc035_typ 9 x 1 11 gatesnor03_2x tsmc035_typ 1 x 1 1 gatesnor04 tsmc035_typ 1 x 1 1 gatesoai21 tsmc035_typ 41 x 1 51 gatesoai22 tsmc035_typ 31 x 1 46 gatesoai32 tsmc035_typ 1 x 2 2 gatesor02 tsmc035_typ 3 x 1 4 gatesor03 tsmc035_typ 1 x 2 2 gatesor04 tsmc035_typ 1 x 2 2 gatesxnor2 tsmc035_typ 32 x 2 61 gatesxor2 tsmc035_typ 32 x 2 68 gates Number of ports : 132 Number of nets : 663 Number of instances : 560 Number of references to this view : 0Total accumulated area : Number of gates : 1236 Number of accumulated instances : 560d. Sequential ATPG:*****Fault List Statistics*****Fault Class Uncollapsed CollapsedFull (FU) 4590 3112Det_simulation (DS) 4257 2806Posdet (PD) 38 24Unused (UU) 146 146Redundant (RE) 4 4Atpg_untestable (AU) 19 19Unobserved (UO) 124 111Uncontrolled (UC) 2 2Fault coverage 93.16% 90.55%Test coverage 96.31% 95.14%ATPG effectiveness 97.04% 96.10% *****Test Patterns Statistics*****Total Test Cycles Generated = 371Total Test Cycles Simulated = 1747User CPU Time : 1333.8 secondsSystem CPU Time : 3.1 secondsFault Classes:Untestable Faults:Untestable (UT) faults are faults for which no pattern can exist to either detect or possibledetect them. Untestable faults cannot cause functional failures, so the tool excludes them when calculating test coverage. These consist of the following subclasses,1. Unused Faults (UU):The unused fault class includes all faults on circuitry unconnected to any circuit observation point. For example the faults on the Qbar lines of FFs.2. Redundant (RE):The redundant fault class includes faults the test generator considers undetectable. After failing to generate any test for these faults the, the pattern generator performs a special analysis to verify that these faults are undetectable under any conditions.Testsbale Faults:These faults are those which cannot be proven untestable. The testable class contains the following subclasses:1. Detected Faults(DS):These are the faults for which tests have been found by the ATPG tool.2. Posdet (PD):The posdet (possible-detected) fault class includes all faults that fault simulation identifies as possible-detected but not hard detected. A possible-detected fault results from a 0-X or 1-X difference at an observation point.3. ATPG_untestable (AU):The ATPG untestable fault class includes all faults for which the test generator is unable to find a pattern to create a test, and yet cannot prove the fault redundant. Testable faults are put under this category if no test is found due to constraints in the ATPG tool.Example: In the multiplier circuit the faults on the Clock line connected to the counter where placed under this category. 1 AU /ctrl_unit_count_2_/CLK 0 AU /ctrl_unit_count_2_/CLK 1 AU /ctrl_unit_count_3_/CLK 0 AU /ctrl_unit_count_3_/CLK4. Undetected (UD):The undetected fault class includes undetected faults that cannot be proven untestable orATPG_untestable. The undetected class contains two subclasses:- uncontrolled (UC) – faults which can never be activated during pattern simulation, i.e. they are uncontrollable.Example: In the multiplier circuit the sa0 on the ‘Done’ line was placed under this category.- unobserved (UO) - faults whose effects do not propagate to an observable point.e. 32-bit Multiplier with Full Scan:The Full Scan Design was implemented using the DFTAdvisor tool from Mentor GraphicsCircuit Statistics# of Inputs 69# of Outputs 65Critical Path