ELEC 7770 Advanced VLSI Design Spring 2012 A Linear Programming Solution to Clock Constraint ProblemA General Sequential CircuitA Level-Sensitive LatchAlternative ImplementationData Must be Stable Before Latch ClosesData and Clock ParametersDesign With Level-Sensitive LatchesEdge-Triggered Flip-flopA Dynamic ImplementationA Static ImplementationDesign With Edge-Triggered Flip-FlopsSetup Time ConstraintHold Time ConstraintSolving Hold Time Problem (1)Solving Hold Time Problem (2)Solving Hold Time Problem (3)Linear Programming Solution (1)Linear Programming Solution (2)Shift Register Example 1 (Long Path)Shift Register Example 1 (Short Path)Slide 21Shift Register Example 2 (Short Path)Shift Register Example 2 (Long Path)Spring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2012Spring 2012A Linear Programming Solution to Clock A Linear Programming Solution to Clock Constraint ProblemConstraint ProblemVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn University, Auburn, AL 36849ECE Department, Auburn University, Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12/course.htmlhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12/course.htmlSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22A General Sequential CircuitA General Sequential CircuitCombinationalLogicRegistersClockInputs OutputsSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33A Level-Sensitive LatchA Level-Sensitive LatchDCKQQNClock period, TckCKtimeLatch open Latch closed Latch openSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Alternative ImplementationAlternative ImplementationDCKQJ. Segura and C. F. Hawkins, CMOS Electronics, How It Works,How It Fails, Wiley Interscience, 2004, p.137.Spring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Data Must be Stable Before Latch ClosesData Must be Stable Before Latch Closes11001D = 0 → 1 → 1CK = 1 → 1 → 0QQNClock period, TckCKtimeLatch open Latch closed0→1→0→0→1→1→0→0→0→0→1→0→1→1→0→1→0→1→Unstable stateStable datadelaysSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Data and Clock ParametersData and Clock ParametersClock period, TckCKtimeLatch open Latch closedDtimeStable dataStable QQtimeSetup timeHold timeCK-to-Q delaySpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Design With Level-Sensitive LatchesDesign With Level-Sensitive LatchesComb.LogicLevel-sens. Latches PI POComb.LogicLevel-sens. Latches PI POCKSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Edge-Triggered Flip-flopEdge-Triggered Flip-flopDCKQQNClock period, TckCKtimeMaster open Slave openMaster latch Slave latchTrigger edgesSetup timeHold timeCK-to-QSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99A Dynamic ImplementationA Dynamic ImplementationDQCKCKCKCKVDDGNDJ. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout andSimulation, Thomsom, 2006, p. 229.Spring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010A Static ImplementationA Static ImplementationDQCKCKCKCKVDDGNDJ. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout andSimulation, Thomsom, 2006, p. 230.Spring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1111Design With Edge-Triggered Flip-FlopsDesign With Edge-Triggered Flip-FlopsCombinationalLogicFlip-flopsClockInputs OutputsSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1212Setup Time ConstraintSetup Time ConstraintFF i FF jCombinational path delay δ(i,j) ≤ d(i,j) ≤ Δ(i,j)Tsi ThiTqiClock edgetimeTckTsjConstraint: si + Tqi + Δ(i,j) ≤ sj + Tck – Tsj i.e., Δ(i,j) ≤ Tck – Tsj – Tqi + sj – si This is known as long path constraint – prevents zero clockingNote: All times for aFF should be adjustedby its clock skew.Arrive nolater thanthisTraveltimeSkew siSkew sjSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1313Hold Time ConstraintHold Time ConstraintFF i FF jCombinational path delay δ(i,j) ≤ d(i,j) ≤ Δ(i,j)Tsi ThiTqiClock edge (si)timeTckTsjConstraint: si + Tqi + δ(i,j) ≥ sj + Thj i.e., δ(i,j) ≥ Thj – Tqi + sj – si sj – si + ThjThis is known as short path constraint – avoids double clockingNote: All times for aFF should be adjustedby its clock skew.Skew siSkew sjSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1414Solving Hold Time Problem (1)Solving Hold Time Problem (1)PO(FFi)PO(FFj)PI(FFi)PI(FFj)POPIFanout nodeInternal edges (fixed delays)External edges (variable delays)Spring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1515Solving Hold Time Problem (2)Solving Hold Time Problem (2)Variables:Variables:Shortest arrival time at node i = aiShortest arrival time at node i = aiLongest arrival time at node i = AiLongest arrival time at node i = AiBuffer delay on external edge (i,j) = wijBuffer delay on external edge (i,j) = wijConstants:Constants:At PI i: Ai = At PI i: Ai = ΛΛi i and ai = and ai = λλi, i, user specified.user specified.At PI (FF) i: Ai = ai = Tqi At PI (FF) i: Ai = ai = TqiSpring 2012, Feb 27 . . .Spring 2012, Feb 27 . . .ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1616Solving Hold Time Problem (3)Solving Hold Time Problem