ELEC 7770 Advanced VLSI Design Spring 2007 A Linear Programming Solution to Clock Constraint ProblemA General Sequential CircuitA Level-Sensitive LatchAlternative ImplementationData Must be Stable Before Latch ClosesData and Clock ParametersDesign With Level-Sensitive LatchesEdge-Triggered Flip-flopA Dynamic ImplementationA Static ImplementationDesign With Edge-Triggered Flip-FlopsSetup Time ConstraintHold Time ConstraintSolving Hold Time Problem (1)Solving Hold Time Problem (2)Solving Hold Time Problem (3)Linear Programming Solution (1)Linear Programming Solution (2)Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2007Spring 2007A Linear Programming Solution to Clock A Linear Programming Solution to Clock Constraint ProblemConstraint ProblemVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)22A General Sequential CircuitA General Sequential CircuitCombinationalLogicRegistersClockInputs OutputsSpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)33A Level-Sensitive LatchA Level-Sensitive LatchDCKQQNClock period, TckCKtimeLatch open Latch closed Latch openSpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)44Alternative ImplementationAlternative ImplementationDCKQJ. Segura and C. F. Hawkins, CMOS Electronics, How It Works,How It Fails, Wiley Interscience, 2004, p.137.Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)55Data Must be Stable Before Latch ClosesData Must be Stable Before Latch Closes11001D = 0 → 1CK = 1 → 0QQNClock period, TckCKtimeLatch open Latch closed0→1→0→0→1→1→0→0→0→0→1→0→1→1→0→1→0→1→Unstable stateStable datadelaysSpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)66Data and Clock ParametersData and Clock ParametersClock period, TckCKtimeLatch open Latch closedDtimeStable dataStable QQtimeSetup timeHold timeCK-to-Q delaySpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)77Design With Level-Sensitive LatchesDesign With Level-Sensitive LatchesComb.LogicLevel-sens. Latches PI POComb.LogicLevel-sens. Latches PI POCKSpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)88Edge-Triggered Flip-flopEdge-Triggered Flip-flopDCKQQNClock period, TckCKtimeMaster open Slave openMaster latch Slave latchTrigger edgesSetup timeHold timeCK-to-QSpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)99A Dynamic ImplementationA Dynamic ImplementationDQCKCKCKCKVDDGNDJ. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout andSimulation, Thomsom, 2006, p. 229.Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1010A Static ImplementationA Static ImplementationDQCKCKCKCKVDDGNDJ. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout andSimulation, Thomsom, 2006, p. 230.Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1111Design With Edge-Triggered Flip-FlopsDesign With Edge-Triggered Flip-FlopsCombinationalLogicFlip-flopsClockInputs OutputsSpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1212Setup Time ConstraintSetup Time ConstraintFF i FF jCombinational path δ(i,j) ≤ d(i,j) ≤ Δ(i,j)Tsi ThiTqiClock edgetimeTckTsjConstraint: Tqi + Δ(i,j) ≤ Tck – Tsj i.e., Δ(i,j) ≤ Tck – Tsj – Tqi This is known as long path constraint.Note: All times for aFF should be adjustedby its clock skew.Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1313Hold Time ConstraintHold Time ConstraintFF i FF jCombinational path δ(i,j) ≤ d(i,j) ≤ Δ(i,j)Tsi ThiTqiClock edgetimeTckTsjConstraint: Tqi + δ(i,j) ≥ Thj i.e., δ(i,j) ≥ Thj – Tqi ThjThis is known as short path constraint.Note: All times for aFF should be adjustedby its clock skew.Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1414Solving Hold Time Problem (1)Solving Hold Time Problem (1)PO(FFi)PO(FFj)PI(FFi)PI(FFj)POPIFanout nodeInternal edges (fixed delays)External edges (variable delays)Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1515Solving Hold Time Problem (2)Solving Hold Time Problem (2)Variables:Variables:Earliest arrival time at node i = aiEarliest arrival time at node i = aiLongest arrival time at node i = AiLongest arrival time at node i = AiBuffer delays on external edge (i,j) = wijBuffer delays on external edge (i,j) = wijConstants:Constants:At PI i: Ai = At PI i: Ai = ΛΛi i and ai = and ai = λλi, i, user specified.user specified.At PI (FF) i: Ai = ai = Tqi At PI (FF) i: Ai = ai = TqiSpring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)1616Solving Hold Time Problem (3)Solving Hold Time Problem (3)Constraints:Constraints:At PO i: Ai At PO i: Ai ≤ Ri and ai ≥ ri, user defined.≤ Ri and ai ≥ ri, user defined.At PO (FF) i:At PO (FF) i:ai ≥ Thi, short path constraint.ai ≥ Thi, short path constraint.Ai ≤ Tck – Tsi, long path constraint.Ai ≤ Tck – Tsi, long path constraint.Optimization function (a linear approximation to Optimization function (a linear approximation to minimum number of delay buffers):minimum number of delay buffers):minimize minimize ∑ ∑ wijwijall externalall externaledges (i,j)edges (i,j)Spring 07, Mar 20Spring 07, Mar 20ELEC 7770: Advanced VLSI Design