ELEC 7770 Advanced VLSI DesignFinal Exam, May 4, 2007 Total 35 pointsBroun 235, 5:00PM—7:30PMProblem 1: Low-Power Design and Test 6 pointsGive a logic design for a single clock scan flip-flop with following characteristics:(a) Scan-in and scan-out transitions are shielded from the combinational logic of the circuit under test to reduce power consumption during test.(b) Clock is inhibited to reduce power consumption in both normal and test modes whenever possible without affecting the correct operation.(c) Comment on any limitations of your design.Problem 2: BDD and Equivalence Checking 6 pointsManually analyzing circuits A and B, draw their binary decision diagrams (BDD). Convert the BDDs to reduced order BDDs (ROBDDs) to verify whether or not the two circuits are functionally equivalent.Problem 3: Elmore Delay Formula 6 pointsThe feed point on a route of length L that connects the roots of two balanced clock distribution trees divides the route into sections of lengths xL from the root of tree 1 and (1 – x)L from the root of tree 2. If the two trees have been pre-routed for zero skew, then show that for maintaining the zero skew,1.45(t2 – t1) + aL (C2 + bL/2)x = aL (bL + C1 + C2)Where, a = per unit length routing resistanceb = per unit length routing capacitanceC1 = capacitance of tree 1 at its root; its root to leaf delay is t1C2 = capacitance of tree 2 at its root; its root to leaf delay is t2Problem 4: Zero-Skew Clock Design 6 pointsThe physical layout of a chip consists of two unequal area partitions. Clock trees have been routed within each partition to provide zero-skew between all flip-flops. Where should an on-chip clock generator be placed to feed the roots of the two trees via minimal length wiring and maintaining zero-skew clocking for the entire chip? Use the following data:(a) The root to flip-flop delays for the two trees are 5ps and 25ps, respectively.(b) Their root node capacitances are 4pF and 30pF, respectively, in the same order as above.(c) The shortest routable distance between the two clock trees is 1mm.(d) Two wire options are available for clock routing:Wire A: resistance = 50Ω/cm, capacitance = 2pf/cmWire B: resistance = 100Ω/cm, capacitance = 4pf/cmName __________________________________________________________________ELEC 7770 Advanced VLSI DesignFinal Exam, May 4, 2007 Total 35 pointsBroun 235, 5:00PM—7:30PMInstructions: Read all questions before writing your answers and attempt all six (6) questions. Be sure torevise your answers before turning them in. Thank you.Problem 1: Low-Power Design and Test 6 pointsGive a logic design for a single clock scan flip-flop with following characteristics:(a) Scan-in and scan-out transitions are shielded from the combinational logic of the circuit under test to reduce power consumption during test.(b) Clock is inhibited to reduce power consumption in both normal and test modes whenever possible without affecting the correct operation.(c) Comment on any limitations of your design.Problem 2: BDD and Equivalence Checking 6 pointsManually analyzing circuits A and B, draw their binary decision diagrams (BDD). Convert the BDDs to reduced order BDDs (ROBDDs) to verify whether or not the two circuits are functionally equivalent.ELEC7770 Final Exam Problems (May 4, 2007) 1 of 3F1a bF2a bName __________________________________________________________________Problem 3: Elmore Delay Formula 6 pointsThe feed point on a route of length L that connects the roots of two balanced clock distribution trees divides the route into sections of lengths xL from the root of tree 1 and (1– x)L from the root of tree 2. If the two trees have been pre-routed for zero skew, then show that for maintaining the zero skew, 1.45(t2 – t1) + aL (C2 + bL/2) x = aL (bL + C1 + C2)Where, a = per unit length routing resistanceb = per unit length routing capacitanceC1 = capacitance of tree 1 at its root; its root to leaf delay is t1C2 = capacitance of tree 2 at its root; its root to leaf delay is t2Problem 4: Zero-Skew Clock Design 6 pointsThe physical layout of a chip consists of two unequal area partitions. Clock trees have been routed within each partition to provide zero-skew between all flip-flops. Where should an on-chip clock generator be placed to feed the roots of the two trees via minimallength wiring and maintaining zero-skew clocking for the entire chip? Use the following data:(a) The root to flip-flop delays for the two trees are 5ps and 25ps, respectively.(b) Their root node capacitances are 4pF and 30pF, respectively, in the same order as above.(c) The shortest routable distance between the two clock trees is 1mm.(d) Two wire options are available for clock routing:Wire A: resistance = 50Ω/cm, capacitance = 2pf/cmWire B: resistance = 100Ω/cm, capacitance = 4pf/cmProblem 5: Fault-tolerant Design for SEU 6 pointsA 32-bit bus, transmitting clocked data, is to be protected against single-event upset (SEU). Design a fault tolerant system for the receiving end with following characteristics:(a) Bus output is received in a clocked parallel input register.(b) Register value is correct if no SEU effects are present and a resend signal remains false.(c) In case any bits are affected by SEU, the register holds the previous correctly received vector and a resend signal is generated.You can use either time or space redundancy. ELEC7770 Final Exam Problems (May 4, 2007) 2 of 3Name __________________________________________________________________Problem 6: Fault-Tolerance 6 pointsIn a triple modular redundancy (TMR) system the error probability for each input signal is e. Find the error probability for the output. Show that the output error probability will be 3e2 for very small values of e. What is the range of input error probabilities (e) for which TMR is ineffective (actually, harmful)?ELEC7770 Final Exam Problems (May 4, 2007) 3 of