Timing AnalysisNeed for Timing AnalysisPrimitive device delay modelsMethods of Timing AnalysisStatic Timing AnalysisSlide 6Area Optimized Vs Delay OptimizedTools to perform Timing AnalysisELDO Design FlowProcedureLeonardoFurther WorkMach TA Post Layout Design FlowQuestions??SuggestionsTiming AnalysisTiming Analysis Instructor: Dr. Vishwani D. Agrawal ELEC 7770 Advanced VLSI Design Team ProjectNeed for Timing AnalysisNeed for Timing AnalysisHigh-performance integrated circuits High-performance integrated circuits have traditionally been characterized have traditionally been characterized by the clock frequency at which they by the clock frequency at which they operate.operate. While timing measurements can While timing measurements can theoretically be performed using a theoretically be performed using a rigorous circuit simulation, such an rigorous circuit simulation, such an approach is liable to be too slow to approach is liable to be too slow to be practical. be practical.Primitive device delay modelsA primitive logic gate has an intrinsic delay.Methods of Timing AnalysisMethods of Timing AnalysisStatic Timing analysis after Static Timing analysis after Synthesis (Pre-Layout Analysis)Synthesis (Pre-Layout Analysis)Static Timing analysis after Static Timing analysis after Place and Route (also called as Place and Route (also called as Post-Layout Analysis)Post-Layout Analysis)Static Timing AnalysisStatic Timing Analysis Only two kinds of timing errors are Only two kinds of timing errors are possible in such a system:possible in such a system:A A hold time violationhold time violation, when a signal , when a signal arrives too early, and advances one arrives too early, and advances one clock cycle before it should. clock cycle before it should. A A setup time violationsetup time violation, when a , when a signal arrives too late, and misses signal arrives too late, and misses the time when it should advance. the time when it should advance.Area Optimized Vs Delay Area Optimized Vs Delay OptimizedOptimized From the Synthesis report of the From the Synthesis report of the Area and Delay Optimized Area and Delay Optimized versions, the Area Optimized versions, the Area Optimized version has lesser Area and version has lesser Area and Delay compared to the Delay Delay compared to the Delay Optimized version.Optimized version.Tools to perform Timing Tools to perform Timing AnalysisAnalysisQuickSimQuickSimMach TAMach TAEldoEldoLeonardo (Results from the Leonardo (Results from the Synthesis)Synthesis)ELDO Design FlowELDO Design FlowProcedureProcedureExtract the schematic from the Extract the schematic from the Netlist.Netlist.Export it as a Spice format.Export it as a Spice format.Force vectors to observe the Force vectors to observe the critical path from the simulation critical path from the simulation results files.results files.Find the critical path from the Find the critical path from the Waveform Viewer (EZWAVE)Waveform Viewer (EZWAVE)LeonardoLeonardoThe Delays from the Area The Delays from the Area Optimized netlist shows that the Optimized netlist shows that the CPU design has a critical path CPU design has a critical path that has a delay of 13.13nsthat has a delay of 13.13nsThis is just an estimate of the This is just an estimate of the pre-layout timing analysis. This pre-layout timing analysis. This delay may differ based on the delay may differ based on the level of optimization. level of optimization.Further WorkFurther WorkThe Post layout incorporates The Post layout incorporates both the block and routing both the block and routing delays as a final analysis of the delays as a final analysis of the design’s timing constraints.design’s timing constraints.Post layout simulation is a better Post layout simulation is a better parameter to find the maximum parameter to find the maximum operational frequency and operational frequency and behavior of the circuit.behavior of the circuit.Mach TA Post Layout Mach TA Post Layout Design Flow Design FlowQuestions??Questions??SuggestionsSuggestionsTechnology that is supported by Technology that is supported by the timing analysers.the timing analysers.32-bit Processor requires 32-bit Processor requires simulation of few days to simulation of few days to perform the timing and power perform the timing and power analysis. A 16-bit processor analysis. A 16-bit processor would have been a better would have been a better choice.