ELEC 7770 Advanced VLSI Design Spring 2012 Gate SizingClock DistributionClock PowerDelay of a CMOS GateReq, Cg, Cint, and Width SizingEffective Fan-out, fSizing an Inverter ChainMinimum Delay SizingSlide 9Sizing for Energy MinimizationSummarySpring 2012, Mar 5Spring 2012, Mar 5ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)11ELEC 7770ELEC 7770Advanced VLSI DesignAdvanced VLSI DesignSpring 2012Spring 2012Gate SizingGate SizingVishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher ProfessorECE Department, Auburn UniversityECE Department, Auburn UniversityAuburn, AL 36849Auburn, AL [email protected]@eng.auburn.eduhttp://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr12Clock DistributionClock DistributionclockSpring 2012, Mar 5Spring 2012, Mar 522ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Clock PowerClock PowerPclk= CLVDD2f + CLVDD2f / λ + CLVDD2f / λ2 + . . .stages – 1 1= CLVDD2f Σ ─ n= 0 λnwhere CL = total load capacitanceλ = constant fanout at each stage in distribution networkClock consumes about 40% of total processor power.Spring 2012, Mar 5Spring 2012, Mar 533ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Delay of a CMOS GateDelay of a CMOS GateCMOSgateCLCgCintPropagation delay through the gate:tp= 0.69 Req(Cint + CL)≈ 0.69 ReqCg(1 + CL /Cg)= tp0(1 + CL /Cg)Gate capacitanceIntrinsic capacitanceSpring 2012, Mar 5Spring 2012, Mar 544ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)RReqeq, , CCgg, , CCintint, , andand Width SizingWidth SizingRReqeq: equivalent resistance of “on” transistor, : equivalent resistance of “on” transistor, proportional to proportional to L/W; scales as L/W; scales as 11/S, /S, S S = sizing = sizing factorfactorCCgg: gate capacitance, proportional to : gate capacitance, proportional to CCoxoxWLWL; ; scales as Sscales as SCCintint: intrinsic output capacitance ≈ : intrinsic output capacitance ≈ CCgg, for , for submicron processessubmicron processes ttp0p0: intrinsic delay = 0.69: intrinsic delay = 0.69RReqeqCCgg; ; independent of independent of sizingsizingSpring 2012, Mar 5Spring 2012, Mar 555ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Effective Fan-out, Effective Fan-out, ffEffective fan-out is defined as the ratio Effective fan-out is defined as the ratio between the external load capacitance and between the external load capacitance and the input capacitance:the input capacitance:ff==CCLL/C/Cggttpp==ttp0p0(1 + (1 + ff ) )Spring 2012, Mar 5Spring 2012, Mar 566ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Sizing an Inverter ChainSizing an Inverter ChainCg1Cg2CL1 2 NCg2= f2Cg1 tp1= tp0 (1 + Cg2/Cg1) tp2= tp0 (1 + Cg3/Cg2)N N tp = Σ tpj= tp0Σ (1 + Cgj+1/Cgj) j=1 j=1Spring 2012, Mar 5Spring 2012, Mar 577ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Minimum Delay SizingMinimum Delay SizingEquate partial derivatives of tp with respect to Cgj to 0:1/Cg1 – Cg3/Cg22 = 0, etc.or Cg22 = Cg1×Cg3, etc. i.e., gate capacitance is geometric mean of forward and backward gate capacitances.Also, Cg2/Cg1 = Cg3/Cg2, etc. i.e., all stages are sized up by the same factor f with respect to the preceding stage:CL/Cg1 = F = fN, tp = Ntp0(1 + F1/N)Spring 2012, Mar 5Spring 2012, Mar 588ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Minimum Delay SizingMinimum Delay SizingEquate partial derivatives of tp with respect to N to 0: dNtp0(1 + F1/N) ───────── = 0dNi.e., F1/N – F1/N(ln F)/N = 0or ln F1/N = ln f = 1 → f = e = 2.7 and N = ln FSpring 2012, Mar 5Spring 2012, Mar 599ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)Sizing for Energy MinimizationSizing for Energy MinimizationMain idea: For a given circuit, reduce energy consumption by reducing the supply voltage. This will increase delay. Compensate the delay increase by transistor sizing.Ref: J. M. Rabaey, A. Chandrakasan and B. Nikolić,Digital Integrated Circuits, Second Edition, Upper Saddle River, New Jersey: Pearson Education, 2003, Section 5.4.Spring 2012, Mar 5Spring 2012, Mar 51010ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal)SummarySummaryDevice sizing combined with supply voltage Device sizing combined with supply voltage reduction reduces energy consumption.reduction reduces energy consumption.For large fan-out energy reduction by a factor of For large fan-out energy reduction by a factor of 10 is possible.10 is possible.An exception is An exception is F F = 1 case, where the minimum = 1 case, where the minimum size device is also the most effective one.size device is also the most effective one.Oversizing the devices increases energy Oversizing the devices increases energy consumption.consumption.Spring 2012, Mar 5Spring 2012, Mar 51111ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design