Due: Tuesday, Apr. 25, 2008ELEC 7770-001, Spring 2008Class ProjectAssigned: Tuesday, Apr. 15, 2008Due: Tuesday, Apr. 25, 2008The following figure shows the architecture of a 32-bit unsigned integer multiplier:It consists of the following parts:1. A 32-bit multiplicand register that receives a parallel 32-bit primary input.2. A 64-bit product register, whose lower order 32 bits initially hold the multipliersupplied as a parallel 32-bit primary input. The entire 64 bits form the product as parallel64-bit primary output.3. A 32 bit integer adder with two 32-bit positive integer operand inputs and a 32-bit sumoutput. In addition, it has a one-bit overflow (OF) signal that is a primary output of thecircuit.ELEC7770 Class Project Page 1 of 2 64-bit product register Multiplicand32323232-bit AdderControl: Do32 timesTest LSBshiftright 00000 . . . 00000 32-bit multiplierInitialized product registerAdd if LSB=1OFCK STARTDONE4. Control logic: Begins on START = 1, initializes most significant 32 bits of productregister to 0, and carries out 32 iterations. Sets primary output DONE = 1 after theiterations are completed.5. Clock (CK): A common primary input clock is supplied to control and all registers.Do the following:a. Read and understand the function of the multiplier. Work out an example by hand toverify the algorithm.b. Encode the circuit in VHDL or Verilog, simulate and verify some test cases. Write asummary report on verification. Do not include printouts.c. Assuming that timing is not critical in this application, synthesize logic for minimumarea. Verify again. Select an available technology and determine the critical path delay.Report circuit statistics, number of PI, PO, flip-flops, gates, delay, etc.d. Generate test vectors in the sequential mode. List the number of test vectors, stuck-atfault coverage, categorize any untested faults giving reasons.e. Insert scan and regenerate tests. List numbers of combinational test vectors, scan testcycles including scan register tests, fault coverage including faults in flip-flops, untestedfaults with reasons. Determine gate overhead of scan and compare with estimatedoverhead.ELEC7770 Class Project Page 2 of
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