Mixed Logic Introduction Mixed logic is a gate level design methodology used in industry It allows a digital logic circuit designer the functional description of the circuit from its physical implementation For example consider the function F A B This is a functional description Two possible physical implementations are listed below one using a NAND gate and inverters the other using a NOR gate and inverters A B NAND A F B NOR F Both of the above circuits implement the same function but are different physical implementations Which is easier to read Ideally the implementation of the circuit should not affect your ability to figure out what the circuit does The goal of mixed logic design is to 1 Separate what the circuit does from how it does it and 2 support self documenting circuits Analysis Before getting into the details of how to design a mixed logic circuit let us modify the circuit of the preceeding example to see how mixed logic notation works Using mixed logic notation the above circuits are now illustrated as A B NAND A F B NOR F Note the vertical bars with the bubbles in both circuits They do not represent physical circuit elements they are simply a form of notation To read a circuit using mixed logic notation 1 Ignore all bubbles on logic gates and inverters This means a Read all NANDs and ANDs as ANDs b read all NORs and ORs as ORs and c ignore all inverters 2 Wherever you see a vertical bar with a bubble take the complement 1 Thus when reading the circuit left to right a bar should exist everywhere that a complement exists in the corresponding logic equation By not worry about everywhere a physical inversion takes place it is much easier to read the function implemented by the circuit In both examples above A is complemented yielding A Ignoring all inverters and treating both logic gates as an AND the output of the gate is AB Inverting the output by the vertical bar after the logic gates results in AB Design Mixed logic design is based on the key observation of DeMorgan s theorem logical operations have equivalencies when their inputs and outputs are inverted DeMorgan s square shown below illustrates the equivalencies of the four basic gate types invert output invert input AND AB 00 01 10 11 NAND AB 00 01 10 11 0 0 0 1 1 1 1 0 NOR AB 00 01 10 11 OR AB 00 01 10 11 1 0 0 0 0 1 1 1 Inverting the output of the gate moves horizontally in the square Moving vertically is accomplished by inverting all gate inputs turning the truth table upside down Each of the four fundamental gates types has both an AND based and OR based functional equivalency based on DeMorgan s theorem You have already seen this for NAND and NOR gates but it applies to AND and OR gates as well While it may seem counterintuitive to draw an AND gate as an OR body with inverted inputs and outputs this variation makes mixed logic design possible 2 Design Example 1 Design a logic circuit for the function F A B C If implemented in a straightforward manner using traditional gate symbols its implementation would be A B F C What if we wanted to implement it using just NAND gates Or only NAND and NOR gates Or any other constraint on what logic gates are used for the physical implementation The basic design rules for implementing a mixed logic design are 1 All logic operations in the function sum and product become gate bodies in the circuit a implement all OR operations in the logical function using the OR equivalency of the logic gate and b implement all AND operations in the logical function using the AND equivalency of the logic gate Note that you can use any of the basic logic gates NAND NOR AND OR depending on your design constraints 2 Draw vertical bars in the circuit where all complements in the logical function occur Draw a bubble on each bar 3 All bubbles in the circuit should be paired so that they cancel out A bubble may be paired with a another bubble on a logic gate or b a bubble on a vertical bar The vertical bars with bubble do not represent physical devices like inverters they are just a form of notation to represent a complement in the underlying function Anywhere a pairing of a bubble is not possible place an inverter Now your circuit implementation is complete To illustrate mixed logic design we will implement the function above four different ways using NAND gates and inverters NOR gates and inverters AND gates and inverters and OR gates and inverters First draw the circuit graphically this is not a physical implementation using AND OR gates for the operations and the vertical bars for the complement As a reminder F A B C A B F C 3 Now let s design it using just NAND gates and inverters 1 Implement the AND and OR operations of the circuit using the corresponding equivalencies of the NAND gate A B F C 2 Draw vertical bars with bubble in the circuit where all complements of the logic function occur Draw a bubble on each bar A B F C 3 All bubbles in the circuit should be paired so that they cancel out A bubble may be paired with a another bubble on a logic gate or b a bubble on a vertical bar A B F C You re done You ve now implemented the circuit using 2 NAND gates and 3 inverters which requires 14 transistors 4 each for the NAND gates 2 each for the inverters The circuit is also self documenting in that by ignoring the inverters and bubbles on the gates and just paying attention to the vertical bars you can easily read off the function being implemented The figure below shows 4 different circuit implementations of this function each using a different type of gate NAND NOR AND OR All circuits implement the same function The first is the example that you just saw Also shown with each circuit is the transistor count for that particular implementation 4 A B F NAND 14 F NOR 14 F AND 18 F OR 14 C A B C A B C A B C Note that three of the four circuits have similar transistor counts while the AND based implementation requires more Why would you choose a particular implementation There are three general reasons 1 To reduct transistor count 2 Component reuse Prior to the development of programmable logic digital circuit boards were implemented entirely with chips integrated circuits or ICs that would have a fixed number of gates on them For example an IC called a 7400 is a quad 2 input NAND gate It has 4 NAND gates on it that can be wired up to other ICs If the designer had one spare NAND gate unallocated on an IC she may choose to fit it into a circuit design rather than …