Review Exceptions Traps and Interrupts A system call instruction causes a synchronous exception or trap CS162 Operating Systems and Systems Programming Lecture 13 In fact often called a software trap instruction Other sources of synchronous exceptions Divide by zero Illegal instruction Bus error bad address e g unaligned access Segmentation Fault address out of range Page Fault for illusion of infinite sized memory Address Translation con t Caches and TLBs Interrupts are Asynchronous Exceptions Examples timer disk ready network etc Interrupts can be disabled traps cannot October 17 2005 Prof John Kubiatowicz http inst eecs berkeley edu cs162 On system call exception or interrupt Hardware enters kernel mode with interrupts disabled Saves PC then jumps to appropriate handler in kernel For some processors x86 processor also saves registers changes stack etc Actual handler typically saves registers other CPU state and switches to kernel stack 10 17 05 Kubiatowicz CS162 UCB Fall 2005 Lec 13 2 Review Four Segments 16 bit addresses Seg 15 14 13 Offset Virtual Address Format 0 Seg ID 0 code 1 data 2 shared 3 stack 0x0000 0x0000 0x4000 0x4000 0x4800 0x5C00 Base 0x4000 0x4800 0xF000 0x0000 Review Implementation of Multi Segment Model Limit 0x0800 0x1400 0x1000 0x3000 Might be shared 0x8000 Space for Other Apps 0xC000 0xF000 Virtual Address Space 10 17 05 Physical Address Space Kubiatowicz CS162 UCB Fall 2005 Shared with Other Apps Lec 13 3 Virtual Seg Offset Address Base0 Base1 Base2 Base3 Base4 Base5 Base6 Base7 Limit0 Limit1 Limit2 Limit3 Limit4 Limit5 Limit6 Limit7 V V V N V N N V Error Physical Address Segment map resides in processor Segment number mapped into base limit pair Base added to offset to generate physical address Error check catches offset out of range As many chunks of physical memory as entries Segment addressed by portion of virtual address However could be included in instruction instead x86 Example mov es bx ax What is V N Can mark segments as invalid requires check as well 10 17 05 Kubiatowicz CS162 UCB Fall 2005 Lec 13 4 Review How to Implement Paging Virtual Virtual Address Page Offset PageTablePtr PageTableSize Goals for Today page page page page page page Access Error 0 V R 1 V R 2 V R W 3 V R W N 4 5 V R W Physical Page Offset Physical Address Finish discussion of Address Translation Caching and TLBs Check Perm Access Error Page Table One per process Resides in physical memory Contains physical page and permission for each virtual page Permissions include Valid bits Read Write etc Virtual address mapping Offset from Virtual address copied to Physical Address Example 10 bit offset 1024 byte pages Virtual page is all remaining bits Example for 32 bits 32 10 22 bits i e 4 million entries Physical page copied from table into physical address Check Page Table bounds and permissions 10 17 05 Kubiatowicz CS162 UCB Fall 2005 Lec 13 5 Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and Gagne 10 17 05 Kubiatowicz CS162 UCB Fall 2005 Another common example two level page table Multi level Translation What about a tree of tables Lowest level page table memory still allocated with bitmap Higher levels often segmented 10 bits 10 bits Virtual Virtual Virtual Address P1 index P2 index 12 bits Physical Physical Address Page Virtual Seg Base0 Base1 Base2 Base3 Base4 Base5 Base6 Base7 Virtual Page Limit0 Limit1 Limit2 Limit3 Limit4 Limit5 Limit6 Limit7 V V V N V N N V Offset page page page page page page 0 V R 1 V R 2 V R W 3 V R W N 4 5 V R W Access Error Physical Page Offset Physical Address 4 bytes Tree of Page Tables Tables fixed size 1024 entries Check Perm On context switch save single PageTablePtr register Access Error Contents of top level segment registers for this example Pointer to top level table page table Kubiatowicz CS162 UCB Fall 2005 4KB PageTablePtr What must be saved restored on context switch 10 17 05 Offset Offset Could have any number of levels Example top segment Virtual Address Lec 13 6 Lec 13 7 Sometimes top level page tables called directories Intel Each entry called a surprise Page Table Entry PTE 10 17 05 4 bytes Kubiatowicz CS162 UCB Fall 2005 Lec 13 8 What is in a PTE What is in a Page Table Entry or PTE Pointer to next level page table or to actual page Permission bits valid read only read write write only Example Intel x86 architecture PTE Address same format previous slide 10 10 12 bit offset Intermediate page tables called Directories 10 17 05 PCD P W U PWT PCD A D L Free 0 L D A UW P OS 11 9 8 7 6 5 4 3 2 1 0 PWT Page Frame Number Physical Page Number 31 12 Present same as valid bit in other architectures Writeable User accessible Page write transparent external cache write through Page cache disabled page cannot be cached Accessed page has been accessed recently Dirty PTE only page has been modified recently L 1 4MB page directory only Bottom 22 bits of virtual address serve as offset Kubiatowicz CS162 UCB Fall 2005 Lec 13 9 Examples of how to use a PTE How do we use the PTE Invalid PTE can imply different things Region of address space is actually invalid or Page directory is just somewhere else than memory Validity checked first OS can use other say 31 bits for location info Usage Example Demand Paging Keep only active pages in memory Place others on disk and mark their PTEs invalid Usage Example Copy on Write UNIX fork gives copy of parent address space to child Address spaces disconnected after child created How to do this cheaply Make copy of parent s page tables point at same memory Mark entries in both sets of page tables as read only Page fault on write creates two copies Usage Example Zero Fill On Demand New data pages must carry no information say be zeroed Mark PTEs as invalid page fault on use gets zeroed page Often OS creates zeroed pages in background 10 17 05 Kubiatowicz CS162 UCB Fall 2005 How is the translation accomplished CPU Virtual Addresses MMU Multi level Translation Analysis Physical Addresses Pros Only need to allocate as many page table entries as we need for application In other wards sparse address spaces are easy What exactly happens inside MMU One possibility Hardware Tree Traversal For each virtual address takes page table base pointer and traverses the page table in hardware Generates a Page Fault if it encounters invalid PTE Fault handler will decide what to do More on this next lecture Pros Relatively fast but still many memory accesses Cons Inflexible Complex
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