CS162Operating Systems andSystems ProgrammingLecture 13Address Translation (con’t)Caches and TLBsOctober 17, 2005Prof. John Kubiatowiczhttp://inst.eecs.berkeley.edu/~cs162Lec 13.210/17/05Kubiatowicz CS162 ©UCB Fall 2005Review: Exceptions: Traps and Interrupts• A system call instruction causes a synchronous exception (or “trap”)– In fact, often called a software “trap” instruction• Other sources of synchronous exceptions:– Divide by zero, Illegal instruction, Bus error (bad address, e.g. unaligned access)– Segmentation Fault (address out of range)– Page Fault (for illusion of infinite-sized memory)• Interrupts are Asynchronous Exceptions– Examples: timer, disk ready, network, etc….– Interrupts can be disabled, traps cannot!• On system call, exception, or interrupt:– Hardware enters kernel mode with interrupts disabled– Saves PC, then jumps to appropriate handler in kernel– For some processors (x86), processor also saves registers, changes stack, etc.• Actual handler typically saves registers, other CPU state, and switches to kernel stackLec 13.310/17/05Kubiatowicz CS162 ©UCB Fall 2005Review: Four Segments (16 bit addresses)0x30000x00003 (stack)0x10000xF0002 (shared)0x14000x48001 (data)0x08000x40000 (code)LimitBaseSeg ID #OffsetSeg014 13150x40000x00000x80000xC000VirtualAddress SpaceVirtual Address Format0x00000x48000x5C000x40000xF000PhysicalAddress SpaceSpace forOther AppsShared withOther AppsMight be sharedLec 13.410/17/05Kubiatowicz CS162 ©UCB Fall 2005Review: Implementation of Multi-Segment Model• Segment map resides in processor– Segment number mapped into base/limit pair– Base added to offset to generate physical address– Error check catches offset out of range• As many chunks of physical memory as entries– Segment addressed by portion of virtual address– However, could be included in instruction instead:» x86 Example: mov [es:bx],ax. • What is “V/N”?– Can mark segments as invalid; requires check as wellBase0 Limit0 VBase1 Limit1 VBase2 Limit2 VBase3 Limit3 NBase4 Limit4 VBase5 Limit5 NBase6 Limit6 NBase7 Limit7 VOffsetSeg #VirtualAddressBase2 Limit2 V+PhysicalAddress>ErrorLec 13.510/17/05Kubiatowicz CS162 ©UCB Fall 2005Physical AddressOffsetReview: How to Implement Paging?• Page Table (One per process)– Resides in physical memory– Contains physical page and permission for each virtual page» Permissions include: Valid bits, Read, Write, etc• Virtual address mapping– Offset from Virtual address copied to Physical Address» Example: 10 bit offset ⇒ 1024-byte pages– Virtual page # is all remaining bits» Example for 32-bits: 32-10 = 22 bits, i.e. 4 million entries» Physical page # copied from table into physical address– Check Page Table bounds and permissionsOffsetVirtualPage #Virtual Address:AccessError>PageTableSizePageTablePtrpage #0page #2page #3page #4page #5V,Rpage #1V,RV,R,WV,R,WNV,R,Wpage #1V,RCheck PermAccessErrorPhysicalPage #Lec 13.610/17/05Kubiatowicz CS162 ©UCB Fall 2005Goals for Today• Finish discussion of Address Translation• Caching and TLBsNote: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne Lec 13.710/17/05Kubiatowicz CS162 ©UCB Fall 2005• What about a tree of tables?– Lowest level page table⇒memory still allocated with bitmap– Higher levels often segmented• Could have any number of levels. Example (top segment):• What must be saved/restored on context switch?– Contents of top-level segment registers (for this example)– Pointer to top-level table (page table)Multi-level Translationpage #0page #1page #3page #4page #5V,RV,Rpage #2V,R,WV,R,WNV,R,WOffsetPhysical AddressVirtual Address:OffsetVirtualPage #VirtualSeg #Base0 Limit0 VBase1 Limit1 VBase2 Limit2 VBase3 Limit3 NBase4 Limit4 VBase5 Limit5 NBase6 Limit6 NBase7 Limit7 VBase2 Limit2 VAccessError>page #2V,R,WPhysicalPage #Check PermAccessErrorLec 13.810/17/05Kubiatowicz CS162 ©UCB Fall 2005PhysicalAddress:OffsetPhysicalPage #4KBAnother common example: two-level page table10 bits 10 bits 12 bitsVirtual Address:OffsetVirtualP2 indexVirtualP1 index4 bytesPageTablePtr• Tree of Page Tables• Tables fixed size (1024 entries)– On context-switch: save single PageTablePtr register• Sometimes, top-level page tables called “directories” (Intel)• Each entry called a (surprise!) Page Table Entry (PTE)4 bytesLec 13.910/17/05Kubiatowicz CS162 ©UCB Fall 2005What is in a PTE?• What is in a Page Table Entry (or PTE)?– Pointer to next-level page table or to actual page– Permission bits: valid, read-only, read-write, write-only• Example: Intel x86 architecture PTE:– Address same format previous slide (10, 10, 12-bit offset)– Intermediate page tables called “Directories”P: Present (same as “valid” bit in other architectures) W: WriteableU: User accessiblePWT: Page write transparent: external cache write-throughPCD: Page cache disabled (page cannot be cached)A: Accessed: page has been accessed recentlyD: Dirty (PTE only): page has been modified recentlyL: L=1⇒4MB page (directory only).Bottom 22 bits of virtual address serve as offsetPage Frame Number(Physical Page Number)Free(OS)0 L D APCDPWTU W P01234567811-931-12Lec 13.1010/17/05Kubiatowicz CS162 ©UCB Fall 2005Examples of how to use a PTE• How do we use the PTE?– Invalid PTE can imply different things:» Region of address space is actually invalid or » Page/directory is just somewhere else than memory– Validity checked first» OS can use other (say) 31 bits for location info• Usage Example: Demand Paging– Keep only active pages in memory– Place others on disk and mark their PTEs invalid• Usage Example: Copy on Write– UNIX fork gives copyof parent address space to child» Address spaces disconnected after child created– How to do this cheaply? » Make copy of parent’s page tables (point at same memory)» Mark entries in both sets of page tables as read-only» Page fault on write creates two copies • Usage Example: Zero Fill On Demand– New data pages must carry no information (say be zeroed)– Mark PTEs as invalid; page fault on use gets zeroed page– Often, OS creates zeroed pages in backgroundLec 13.1110/17/05Kubiatowicz CS162 ©UCB Fall 2005How is the translation accomplished?• What, exactly happens inside MMU?• One possibility: Hardware Tree Traversal– For each virtual address, takes page table base pointer and traverses the page table in
View Full Document
Unlocking...