CS162 Operating Systems and Systems Programming Lecture 12 Protection (continued) Address TranslationReview: Important Aspects of Memory MultiplexingReview: General Address TranslationReview: Simple Segmentation: Base and Bounds (CRAY-1)Review: Cons for Simple Segmentation MethodGoals for TodayMore Flexible SegmentationImplementation of Multi-Segment ModelIntel x86 Special RegistersExample: Four Segments (16 bit addresses)Example of segment translationAdministriviaObservations about SegmentationSchematic View of SwappingPaging: Physical Memory in Fixed Size ChunksHow to Implement Paging?What about Sharing?Simple Page Table DiscussionMulti-level TranslationWhat about Sharing (Complete Segment)?Another common example: two-level page tableMulti-level Translation AnalysisInverted Page TableDual-Mode OperationFor Protection, Lock User-Programs in AsylumHow to get from KernelUserUserKernel (System Call)System Call ContinuedUserKernel (Exceptions: Traps and Interrupts)Additions to MIPS ISA to support Exceptions?Closing thought: Protection without HardwareSummary (1/2)Summary (2/2)CS162Operating Systems andSystems ProgrammingLecture 12Protection (continued)Address TranslationOctober 7, 2009Prof. John Kubiatowiczhttp://inst.eecs.berkeley.edu/~cs162Lec 12.210/7/09 Kubiatowicz CS162 ©UCB Fall 2009Review: Important Aspects of Memory Multiplexing•Controlled overlap:–Separate state of threads should not collide in physical memory. Obviously, unexpected overlap causes chaos!–Conversely, would like the ability to overlap when desired (for communication)•Translation: –Ability to translate accesses from one address space (virtual) to a different one (physical)–When translation exists, processor uses virtual addresses, physical memory uses physical addresses–Side effects:»Can be used to avoid overlap»Can be used to give uniform view of memory to programs•Protection:–Prevent access to private memory of other processes»Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc).»Kernel data protected from User programs»Programs protected from themselvesLec 12.310/7/09 Kubiatowicz CS162 ©UCB Fall 2009Review: General Address TranslationProg 1VirtualAddressSpace 1Prog 2VirtualAddressSpace 2CodeDataHeapStackCodeDataHeapStackData 2Stack 1Heap 1OS heap & StacksCode 1Stack 2Data 1Heap 2Code 2OS codeOS dataTranslation Map 1 Translation Map 2Physical Address SpaceLec 12.410/7/09 Kubiatowicz CS162 ©UCB Fall 2009Review: Simple Segmentation: Base and Bounds (CRAY-1)•Can use base & bounds/limit for dynamic address translation (Simple form of “segmentation”):–Alter every address by adding “base”–Generate error if address bigger than limit•This gives program the illusion that it is running on its own dedicated machine, with memory starting at 0–Program gets continuous region of memory–Addresses within program do not have to be relocated when program placed in different region of DRAMDRAM>?+BaseLimitCPUVirtualAddressPhysicalAddressYes: Error!Lec 12.510/7/09 Kubiatowicz CS162 ©UCB Fall 2009Review: Cons for Simple Segmentation Method•Fragmentation problem (complex memory allocation)–Not every process is the same size–Over time, memory space becomes fragmented–Really bad if want space to grow dynamically (e.g. heap) •Other problems for process maintenance–Doesn’t allow heap and stack to grow independently–Want to put these as far apart in virtual memory space as possible so that they can grow as needed•Hard to do inter-process sharing–Want to share code segments when possible–Want to share memory between processesprocess 6process 5process 2OSprocess 6process 5OSprocess 6process 5OSprocess 9process 6process 5process 9OSprocess 10Lec 12.610/7/09 Kubiatowicz CS162 ©UCB Fall 2009Goals for Today•Address Translation Schemes–Segmentation–Paging–Multi-level translation–Paged page tables–Inverted page tables•Discussion of Dual-Mode operation•Comparison among optionsNote: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne Note: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne. Many slides generated from my lecture notes by Kubiatowicz.Lec 12.710/7/09 Kubiatowicz CS162 ©UCB Fall 2009More Flexible Segmentation•Logical View: multiple separate segments–Typical: Code, Data, Stack–Others: memory sharing, etc•Each segment is given region of contiguous memory–Has a base and limit–Can reside anywhere in physical memory1324user view ofmemory space 1423physical memory space12Lec 12.810/7/09 Kubiatowicz CS162 ©UCB Fall 2009Implementation of Multi-Segment Model•Segment map resides in processor–Segment number mapped into base/limit pair–Base added to offset to generate physical address–Error check catches offset out of range•As many chunks of physical memory as entries–Segment addressed by portion of virtual address–However, could be included in instruction instead:»x86 Example: mov [es:bx],ax. •What is “V/N”?–Can mark segments as invalid; requires check as wellBase0Limit0 VBase1Limit1 VBase2Limit2 VBase3Limit3 NBase4Limit4 VBase5Limit5 NBase6Limit6 NBase7Limit7 VOffsetSeg #VirtualAddressBase2Limit2 V+PhysicalAddress>ErrorLec 12.910/7/09 Kubiatowicz CS162 ©UCB Fall 2009Intel x86 Special RegistersTypical Segment RegisterCurrent Priority is RPLOf Code Segment (CS)80386 Special RegistersLec 12.1010/7/09 Kubiatowicz CS162 ©UCB Fall 2009Example: Four Segments (16 bit addresses)Seg ID # Base Limit0 (code) 0x40000x08001 (data) 0x48000x14002 (shared)0xF0000x10003 (stack) 0x00000x3000OffsetSeg01413150x40000x00000x80000xC000VirtualAddress SpaceVirtual Address Format0x00000x48000x5C000x40000xF000PhysicalAddress SpaceSpace forOther AppsShared withOther AppsMight be sharedLec 12.1110/7/09 Kubiatowicz CS162 ©UCB Fall 2009Example of segment translationLet’s simulate a bit of this code to see what happens (PC=0x240):•Fetch 0x240. Virtual segment #? 0; Offset? 0x240Physical address? Base=0x4000, so physical addr=0x4240Fetch instruction at 0x4240. Get “la $a0, varx”Move 0x4050 $a0, Move PC+4PC2. Fetch 0x244. Translated to Physical=0x4244. Get “jal strlen”Move 0x0248 $ra (return address!), Move 0x0360 PC3. Fetch 0x360. Translated to Physical=0x4360. Get “li $v0,0”Move 0x0000 $v0, Move PC+4PC4. Fetch 0x364. Translated to
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