CS162Operating Systems andSystems ProgrammingLecture 12Protection (continued)Address TranslationOctober 8, 2007Prof. John Kubiatowiczhttp://inst.eecs.berkeley.edu/~cs162Lec 12.210/8/06Kubiatowicz CS162 ©UCB Fall 2007Review: Important Aspects of Memory Multiplexing• Controlled overlap:– Separate state of threads should not collide in physical memory. Obviously, unexpected overlap causes chaos!– Conversely, would like the ability to overlap when desired (for communication)• Translation: – Ability to translate accesses from one address space (virtual) to a different one (physical)– When translation exists, processor uses virtual addresses, physical memory uses physical addresses– Side effects:» Can be used to avoid overlap» Can be used to give uniform view of memory to programs• Protection:– Prevent access to private memory of other processes» Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc).» Kernel data protected from User programs» Programs protected from themselvesLec 12.310/8/06Kubiatowicz CS162 ©UCB Fall 2007Review: General Address TranslationProg 1VirtualAddressSpace 1Prog 2VirtualAddressSpace 2CodeDataHeapStackCodeDataHeapStackData 2Stack 1Heap 1OS heap & StacksCode 1Stack 2Data 1Heap 2Code 2OS codeOS dataTranslation Map 1 Translation Map 2Physical Address SpaceLec 12.410/8/06Kubiatowicz CS162 ©UCB Fall 2007Goals for Today• Address Translation Schemes– Segmentation– Paging– Multi-level translation– Paged page tables– Inverted page tables• Discussion of Dual-Mode operation• Comparison among optionsNote: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne Note: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne. Many slides generated from my lecture notes by Kubiatowicz.Lec 12.510/8/06Kubiatowicz CS162 ©UCB Fall 2007Review: Simple Segmentation: Base and Bounds (CRAY-1)• Can use base & bounds/limit for dynamic address translation (Simple form of “segmentation”):– Alter every address by adding “base”– Generate error if address bigger than limit• This gives program the illusion that it is running on its own dedicated machine, with memory starting at 0– Program gets continuous region of memory– Addresses within program do not have to be relocated when program placed in different region of DRAMDRAM>?+BaseLimitCPUVirtualAddressPhysicalAddressYes: Error!Lec 12.610/8/06Kubiatowicz CS162 ©UCB Fall 2007Base and Limit segmentation discussion• Provides level of indirection– OS can move bits around behind program’s back– Can be used to correct if program needs to grow beyond its bounds or coalesce fragments of memory• Only OS gets to change the base and limit!– Would defeat protection• What gets saved/restored on a context switch?– Everything from before + base/limit values– Or: How about complete contents of memory (out to disk)? » Called “Swapping”• Hardware cost– 2 registers/Adder/Comparator– Slows down hardware because need to take time to do add/compare on every access• Base and Limit Pros: Simple, relatively fastLec 12.710/8/06Kubiatowicz CS162 ©UCB Fall 2007Cons for Simple Segmentation Method• Fragmentation problem (complex memory allocation)– Not every process is the same size– Over time, memory space becomes fragmented– Really bad if want space to grow dynamically (e.g. heap) • Other problems for process maintenance– Doesn’t allow heap and stack to grow independently– Want to put these as far apart in virtual memory space as possible so that they can grow as needed• Hard to do inter-process sharing– Want to share code segments when possible– Want to share memory between processesprocess 6process 5process 2OSprocess 6process 5OSprocess 6process 5OSprocess 9process 6process 5process 9OSprocess 10Lec 12.810/8/06Kubiatowicz CS162 ©UCB Fall 2007More Flexible Segmentation• Logical View: multiple separate segments– Typical: Code, Data, Stack– Others: memory sharing, etc• Each segment is given region of contiguous memory– Has a base and limit– Can reside anywhere in physical memory1324user view ofmemory space1423physical memory space12Lec 12.910/8/06Kubiatowicz CS162 ©UCB Fall 2007Implementation of Multi-Segment Model• Segment map resides in processor– Segment number mapped into base/limit pair– Base added to offset to generate physical address– Error check catches offset out of range• As many chunks of physical memory as entries– Segment addressed by portion of virtual address– However, could be included in instruction instead:» x86 Example: mov [es:bx],ax. • What is “V/N”?– Can mark segments as invalid; requires check as wellBase0 Limit0 VBase1 Limit1 VBase2 Limit2 VBase3 Limit3 NBase4 Limit4 VBase5 Limit5 NBase6 Limit6 NBase7 Limit7 VOffsetSeg #VirtualAddressBase2 Limit2 V+PhysicalAddress>ErrorLec 12.1010/8/06Kubiatowicz CS162 ©UCB Fall 2007Intel x86 Special RegistersTypical Segment RegisterCurrent Priority is RPLOf Code Segment (CS)80386 Special RegistersLec 12.1110/8/06Kubiatowicz CS162 ©UCB Fall 2007Example: Four Segments (16 bit addresses)0x30000x00003 (stack)0x10000xF0002 (shared)0x14000x48001 (data)0x08000x40000 (code)LimitBaseSeg ID #OffsetSeg014 13150x40000x00000x80000xC000VirtualAddress SpaceVirtual Address Format0x00000x48000x5C000x40000xF000PhysicalAddress SpaceSpace forOther AppsShared withOther AppsMight be sharedLec 12.1210/8/06Kubiatowicz CS162 ©UCB Fall 2007Example of segment translationLet’s simulate a bit of this code to see what happens (PC=0x240):• Fetch 0x240. Virtual segment #? 0; Offset? 0x240Physical address? Base=0x4000, so physical addr=0x4240Fetch instruction at 0x4240. Get “la $a0, varx”Move 0x4050 → $a0, Move PC+4→PC2. Fetch 0x244. Translated to Physical=0x4244. Get “jal strlen”Move 0x0248 → $ra (return address!), Move 0x0360 → PC3. Fetch 0x360. Translated to Physical=0x4360. Get “li $v0,0”Move 0x0000 → $v0, Move PC+4→PC4. Fetch 0x364. Translated to Physical=0x4364. Get “lb $t0,($a0)”Since $a0 is 0x4050, try to load byte from 0x4050Translate 0x4050. Virtual segment #? 1; Offset? 0x50Physical address? Base=0x4800, Physical addr = 0x4850, Load Byte from 0x4850→$t0, Move PC+4→PC0x240 main: la $a0, varx0x244 jal strlen……0x360 strlen: li $v0, 0 ;count0x364 loop: lb $t0, ($a0)0x368 beq $r0,$t1,
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