Review Important Aspects of Memory Multiplexing Controlled overlap CS162 Operating Systems and Systems Programming Lecture 12 Separate state of threads should not collide in physical memory Obviously unexpected overlap causes chaos Conversely would like the ability to overlap when desired for communication Translation Ability to translate accesses from one address space virtual to a different one physical When translation exists processor uses virtual addresses physical memory uses physical addresses Side effects Protection continued Address Translation Can be used to avoid overlap Can be used to give uniform view of memory to programs October 8 2007 Prof John Kubiatowicz http inst eecs berkeley edu cs162 Protection Prevent access to private memory of other processes Different pages of memory can be given special behavior Read Only Invisible to user programs etc Kernel data protected from User programs Programs protected from themselves 10 8 06 Kubiatowicz CS162 UCB Fall 2007 Review General Address Translation Data 2 Code Data Heap Stack Heap 1 Code 1 Stack 2 Prog 1 Virtual Address Space 1 Goals for Today Address Translation Schemes Code Data Heap Stack Stack 1 Prog 2 Virtual Address Space 2 Data 1 Heap 2 Code 2 Lec 12 2 Segmentation Paging Multi level translation Paged page tables Inverted page tables Discussion of Dual Mode operation Comparison among options OS code Translation Map 1 OS data Translation Map 2 Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and Gagne Gagne Many slides generated from my lecture notes by Kubiatowicz OS heap Stacks 10 8 06 Physical Address Space Kubiatowicz CS162 UCB Fall 2007 Lec 12 3 10 8 06 Kubiatowicz CS162 UCB Fall 2007 Lec 12 4 Review Simple Segmentation Base and Bounds CRAY 1 Base Virtual Address CPU Limit DRAM Physical Address Provides level of indirection OS can move bits around behind program s back Can be used to correct if program needs to grow beyond its bounds or coalesce fragments of memory Only OS gets to change the base and limit Yes Error Can use base bounds limit for dynamic address translation Simple form of segmentation Alter every address by adding base Generate error if address bigger than limit This gives program the illusion that it is running on its own dedicated machine with memory starting at 0 Program gets continuous region of memory Addresses within program do not have to be relocated when program placed in different region of DRAM 10 8 06 Base and Limit segmentation discussion Kubiatowicz CS162 UCB Fall 2007 Lec 12 5 Cons for Simple Segmentation Method Fragmentation problem complex memory allocation Would defeat protection What gets saved restored on a context switch Everything from before base limit values Or How about complete contents of memory out to disk Called Swapping Hardware cost 2 registers Adder Comparator Slows down hardware because need to take time to do add compare on every access Base and Limit Pros Simple relatively fast 10 8 06 Kubiatowicz CS162 UCB Fall 2007 More Flexible Segmentation Not every process is the same size Over time memory space becomes fragmented Really bad if want space to grow dynamically e g heap process 6 process 6 process 6 process 6 process 5 process 5 process 5 process 5 process 9 process 9 process 2 OS 4 1 2 3 22 4 3 OS OS user view of memory space Other problems for process maintenance Doesn t allow heap and stack to grow independently Want to put these as far apart in virtual memory space as possible so that they can grow as needed Hard to do inter process sharing Want to share code segments when possible Want to share memory between processes 10 8 06 11 process 10 OS Kubiatowicz CS162 UCB Fall 2007 Lec 12 6 Logical View multiple separate segments physical memory space Typical Code Data Stack Others memory sharing etc Each segment is given region of contiguous memory Lec 12 7 Has a base and limit Can reside anywhere in physical memory 10 8 06 Kubiatowicz CS162 UCB Fall 2007 Lec 12 8 Implementation of Multi Segment Model Virtual Seg Offset Address Base0 Base1 Base2 Base3 Base4 Base5 Base6 Base7 Limit0 Limit1 Limit2 Limit3 Limit4 Limit5 Limit6 Limit7 V V V N V N N V Intel x86 Special Registers Error Physical Address 80386 Special Registers Segment map resides in processor Segment number mapped into base limit pair Base added to offset to generate physical address Error check catches offset out of range As many chunks of physical memory as entries Segment addressed by portion of virtual address However could be included in instruction instead x86 Example mov es bx ax What is V N Can mark segments as invalid requires check as well 10 8 06 Kubiatowicz CS162 UCB Fall 2007 Lec 12 9 Typical Segment Register Current Priority is RPL Of Code Segment CS 10 8 06 Kubiatowicz CS162 UCB Fall 2007 Example Four Segments 16 bit addresses Seg 15 14 13 Offset Virtual Address Format 0 Seg ID 0 code 1 data 2 shared 3 stack 0x0000 0x0000 0x4000 0x4000 0x4800 0x5C00 Base 0x4000 0x4800 0xF000 0x0000 Limit 0x0800 0x1400 0x1000 0x3000 Might be shared 0x8000 Space for Other Apps 0xC000 0xF000 Virtual Address Space 10 8 06 Physical Address Space Kubiatowicz CS162 UCB Fall 2007 Shared with Other Apps Lec 12 11 Lec 12 10 Example of segment translation 0x240 0x244 0x360 0x364 0x368 0x4050 main la a0 varx jal strlen strlen li v0 0 count loop lb t0 a0 beq r0 t1 done varx dw 0x314159 Seg ID 0 code 1 data 2 shared 3 stack Base 0x4000 0x4800 0xF000 0x0000 Limit 0x0800 0x1400 0x1000 0x3000 Let s simulate a bit of this code to see what happens PC 0x240 Fetch 0x240 Virtual segment 0 Offset 0x240 Physical address Base 0x4000 so physical addr 0x4240 Fetch instruction at 0x4240 Get la a0 varx Move 0x4050 a0 Move PC 4 PC 2 Fetch 0x244 Translated to Physical 0x4244 Get jal strlen Move 0x0248 ra return address Move 0x0360 PC 3 Fetch 0x360 Translated to Physical 0x4360 Get li v0 0 Move 0x0000 v0 Move PC 4 PC 4 Fetch 0x364 Translated to Physical 0x4364 Get lb t0 a0 Since a0 is 0x4050 try to load byte from 0x4050 Translate 0x4050 Virtual segment 1 Offset 0x50 Physical address Base 0x4800 Physical addr 0x4850 Load Byte from 0x4850 t0 Move PC 4 PC 10 8 06 Kubiatowicz CS162 UCB Fall 2007 Lec 12 12 Administrivia Midterm I coming up in two days Wednesday 10 10 6 00 9 00pm Should be 2 hour exam with extra time Closed book one page of hand written notes both sides Two testing rooms If your Last Name starts with A P Take Midterm in 141 McCone Midterm Topics Perhaps Topics
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