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Berkeley COMPSCI 162 - Lecture 1

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Who am I CS162 Operating Systems and Systems Programming Lecture 1 Alewife Professor John Kubiatowicz Prof Kubi Background in Hardware Design Alewife project at MIT Designed CMMU Modified SPAR C processor Helped to write operating system Background in Operating Systems What is an Operating System August 27th 2008 Prof John Kubiatowicz http inst eecs berkeley edu cs162 Tessellation Worked for Project Athena MIT OS Developer device drivers network file systems Worked on Clustered High Availability systems CLAM Associates OS lead researcher for the new Berkeley PARLab Tessellation OS More later Peer to Peer OceanStore OceanStore project Store your data for 1000 years Tapestry and Bamboo Find you data around globe Quantum Computing 8 27 08 Goals for Today Well this is just cool but probably not apropos Kubiatowicz CS162 UCB Fall 2008 Lec 1 2 Technology Trends Moore s Law What is an Operating System And what is it not Examples of Operating Systems design Why study Operating Systems Oh and How does this class operate Moore s Law Interactive is important Ask Questions 2X transistors Chip Every 1 5 years Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and Gagne Slides courtesy of Kubiatowicz AJ Shankar George Necula Alex Aiken Eric Brewer Ras Bodik Ion Stoica Doug Tygar and David Wagner 8 27 08 Kubiatowicz CS162 UCB Fall 2008 Lec 1 3 Gordon Moore co founder of Intel predicted in 1965 that the transistor density of semiconductor chips would double roughly every 18 months 8 27 08 Called Moore s Law Microprocessors have become smaller denser and more powerful Kubiatowicz CS162 UCB Fall 2008 Lec 1 4 Societal Scale Information Systems People to Computer Ratio Over Time The world is a large parallel system Microprocessors in everything Vast infrastructure behind them From David Culler Massive Cluster Gigabit Ethernet Internet Connectivity Clusters Scalable Reliable Secure Services Databases Information Collection Remote Storage Online Games Commerce Today Multiple CPUs person MEMS for Sensor 8 27 08 Nets Kubiatowicz CS162 UCB Fall 2008 Lec 1 5 8 27 08 Performance vs VAX 11 780 year 1000 100 25 year Sea change in chip design multiple cores or processors per chip 1 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 VAX 25 year 1978 to 1986 RISC x86 52 year 1986 to 2002 8 27 08 RISC x86 year Kubiatowicz 2002 to present CS162 UCB Fall 2008 Lec 1 7 80 simple cores Two floating point engines core Mesh like network on a chip 100 million transistors 65nm feature size Frequency Voltage Power Bandwidth Performance 3 16 GHz 0 95 V 62W 1 62 Terabits s 1 01 Teraflops 5 1 GHz 1 2 V 175W 2 61 Terabits s 1 63 Teraflops 5 7 GHz 1 35 V 265W 2 92 Terabits s 1 81 Teraflops 52 year 10 Lec 1 6 Intel 80 core multicore chip Feb 2007 3X From Hennessy and Patterson Computer Architecture A Quantitative Approach 4th edition Sept 15 2006 Kubiatowicz CS162 UCB Fall 2008 ManyCore Chips The future is here New Challenge Slowdown in Joy s law of Performance 10000 Approaching 100s ManyCore refers to many processors chip 64 128 Hard to say exact boundary How to program these Use 2 CPUs for video audio Use 1 for word processor 1 for browser 76 for virus checking Parallelism must Kubiatowicz be exploited at all levels CS162 UCB Fall 2008 8 27 08 Lec 1 8 Another Challenge Power Density Computer System Organization Computer system operation One or more CPUs device controllers connect through common bus providing access to shared memory Concurrent execution of CPUs and devices competing for memory cycles Moore s Law Extrapolation Potential power density reaching amazing levels Flip side Battery life very important Moore s law can yield more functionality at equivalent or less total energy consumption 8 27 08 Kubiatowicz CS162 UCB Fall 2008 Lec 1 9 8 27 08 Kubiatowicz CS162 UCB Fall 2008 Functionality comes with great complexity Lec 1 10 Sample of Computer Architecture Topics Input Output and Storage Disks WORM Tape Pentium IV Chipset Emerging Technologies Interleaving Bus protocols DRAM Caches Busses Memory Hierarchy adapters Coherence Bandwidth Latency L2 Cache Memory Controllers I O Devices 8 27 08 Disks Displays Keyboards VLSI L1 Cache Instruction Set Architecture Kubiatowicz CS162 UCB Fall 2008 Addressing Protection Exception Handling Pipelining Hazard Resolution Superscalar Reordering Prediction Speculation Vector Dynamic Compilation Networks Lec 1 11 8 27 08 Network Communication Other Processors Proc RAID Pipelining and Instruction Level Parallelism Kubiatowicz CS162 UCB Fall 2008 Lec 1 12 Increasing Software Complexity Example Some Mars Rover Pathfinder Requirements From MIT s 6 033 course 8 27 08 Kubiatowicz CS162 UCB Fall 2008 Lec 1 13 Pathfinder hardware limitations complexity 20Mhz processor 128MB of DRAM VxWorks OS cameras scientific instruments batteries solar panels and locomotion equipment Many independent processes work together Can t hit reset button very easily Must reboot itself if necessary Always able to receive commands from Earth Individual Programs must not interfere Suppose the MUT Martian Universal Translator Module buggy Better not crash antenna positioning software Further all software may crash occasionally Automatic restart with diagnostics sent to Earth Periodic checkpoint of results saved Certain functions time critical Need to stop before hitting something Must track orbit of Earth for communication 8 27 08 How do we tame complexity Application Different CPU Pentium PowerPC ColdFire ARM MIPS Operating System Different amounts of memory disk Different types of devices Hardware Mice Keyboards Sensors Cameras Fingerprint readers Virtual Machine Interface Physical Machine Interface Software Engineering Problem Different networking environment Cable DSL Wireless Firewalls Questions Does the programmer need to write a single program that performs many independent activities Does every program have to be altered for every piece of hardware Does a faulty program crash everything Does every program have access to all hardware Kubiatowicz CS162 UCB Fall 2008 Lec 1 14 OS Tool Virtual Machine Abstraction Every piece of computer hardware different 8 27 08 Kubiatowicz CS162 UCB Fall 2008 Lec 1 15 Turn hardware software quirks what programmers want need Optimize for convenience utilization security reliability etc For Any OS area e g file systems virtual memory networking scheduling What s the hardware interface physical reality What s the


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Berkeley COMPSCI 162 - Lecture 1

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