Page 1 CS162!Operating Systems and!Systems Programming!Lecture 9!Address Translation"February 16, 2011!Ion Stoica!http://inst.eecs.berkeley.edu/~cs162!Lec 9.2!2/16! Ion Stoica CS162 ©UCB Spring 2011!Review: Important Aspects of Memory Multiplexing"• Controlled overlap:!– Ability to explicitly control whether to processes should share or not a region of memory!• Protection:!– Prevent access to private memory of other processes!» Kernel data protected from User programs!» Programs protected from themselves!» Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc)!• Translation: !– Ability to translate accesses from one address space (virtual) to a different one (physical)!– When translation exists, processor uses virtual addresses, physical memory uses physical addresses!– Side effects:!» Can be used to avoid overlap!» Can be used to give uniform view of memory to programs!Lec 9.3!2/16! Ion Stoica CS162 ©UCB Spring 2011!Goals for Today"• Address Translation Schemes!– Segmentation!– Paging!– Multi-level translation!– Paged page tables!– Inverted page tables!• Discussion of Dual-Mode operation!Note: Some slides and/or pictures in the following are adapted from slides ©2005 Silberschatz, Galvin, and Gagne. Many slides generated from lecture notes by Kubiatowicz."Lec 9.4!2/16! Ion Stoica CS162 ©UCB Spring 2011!Uniprograming: Loading Program in Memory"0x300 00000020 … … 0x900 8C2000C0 0x904 0C000340 0x908 2021FFFF 0x90C 1420FFFF … 8C2000C0 0C000340 2021FFFF 1420FFFF 0x0900"0xFFFF"0x0300"0x0000"00000020 data1: dw 32 … start: lw r1,0(data1) jal checkit loop: addi r1, r1, -1 bnz r1, r0, loop … checkit: … Program view of memory!Memory!Page 2 Lec 9.5!2/16! Ion Stoica CS162 ©UCB Spring 2011!Multiprograming: Where do you load program?"0x300 00000020 … … 0x900 8C2000C0 0x904 0C000340 0x908 2021FFFF 0x90C 1420FFFF … 0x0900"0xFFFF"0x0300"0x0000"data1: dw 32 … start: lw r1,0(data1) jal checkit loop: addi r1, r1, -1 bnz r1, r0, loop … checkit: … Program view of memory!Memory!App X!?!Need address translation!!Lec 9.6!2/16! Ion Stoica CS162 ©UCB Spring 2011!Example of General Address Translation"Prog 1"Virtual"Address"Space 1"Prog 2"Virtual"Address"Space 2"Code"Data"Heap"Stack"Code"Data"Heap"Stack"Data 2"Stack 1"Heap 1"OS heap & "Stacks"Code 1"Stack 2"Data 1"Heap 2"Code 2"OS code"OS data"Translation Map 1" Translation Map 2"Physical Address Space"Lec 9.7!2/16! Ion Stoica CS162 ©UCB Spring 2011!Segmentation with Base and Limit Registers"• Could use base/limit for dynamic address translation (often called “segmentation”):!– Alter address of every load/store by adding “base”!– User allowed to read/write within segment!» Accesses are relative to segment so donʼt have to be relocated when program moved to different segment!– User may have multiple segments available (e.g x86)!» Loads and stores include segment ID in opcode:$!x86 Example: mov [es:bx],ax. !» Operating system moves around segment base pointers as necessary!DRAM"<?"+"Base"Limit"CPU"Virtual"Address"Physical"Address"No: Error!"Lec 9.8!2/16! Ion Stoica CS162 ©UCB Spring 2011!More Flexible Segmentation"• Logical View: multiple separate segments!– Typical: Code, Data, Stack!– Others: memory sharing, etc!• Each segment is given region of contiguous memory!– Has a base and limit!– Can reside anywhere in physical memory!1!3!2!4!user view of memory space !1!4!2!3!physical memory space 1!2!Page 3 Lec 9.9!2/16! Ion Stoica CS162 ©UCB Spring 2011!Implementation of Multi-Segment Model"• Segment map resides in processor!– Segment number mapped into base/limit pair!– Base added to offset to generate physical address!– Error check catches offset out of range!• As many chunks of physical memory as entries!– Segment addressed by portion of virtual address!– However, could be included in instruction instead:!» x86 Example: mov [es:bx],ax. !• What is “V/N”?!– Can mark segments as invalid; requires check as well!Base0" Limit0" V"Base1" Limit1" V"Base2" Limit2" V"Base3" Limit3" N"Base4" Limit4" V"Base5" Limit5" N"Base6" Limit6" N"Base7" Limit7" V"Offset"Seg #"Virtual"Address"Base2" Limit2" V"+"Physical"Address">"Error"Lec 9.10!2/16! Ion Stoica CS162 ©UCB Spring 2011!Example: Four Segments (16 bit addresses)"Seg ID #" Base" Limit"0 (code)" 0x4000" 0x0800"1 (data)" 0x4800" 0x1400"2 (shared)" 0xF000" 0x1000"3 (stack)" 0x0000" 0x3000"Offset"Seg"0"14" 13"15"0x4000"0x0000"0x8000"0xC000"Virtual"Address Space"Virtual Address Format"0x0000"0x4800"0x5C00"0x4000"0xF000"Physical"Address Space"Space for"Other Apps"Shared with"Other Apps"Might "be shared"Lec 9.11!2/16! Ion Stoica CS162 ©UCB Spring 2011!Example of segment translation"Letʼs simulate a bit of this code to see what happens (PC=0x240):!1. Fetch 0x240. Virtual segment #? 0; Offset? 0x240!!Physical address? Base=0x4000, so physical addr=0x4240!!Fetch instruction at 0x4240. Get “la $a0, varx”!!Move 0x4050 → $a0, Move PC+4→PC!2. Fetch 0x244. Translated to Physical=0x4244. Get “jal strlen”$Move 0x0248 → $ra (return address!), Move 0x0360 → PC!3. Fetch 0x360. Translated to Physical=0x4360. Get “li $v0,0”$Move 0x0000 → $v0, Move PC+4→PC!4. Fetch 0x364. Translated to Physical=0x4364. Get “lb $t0,($a0)”$Since $a0 is 0x4050, try to load byte from 0x4050!!Translate 0x4050. Virtual segment #? 1; Offset? 0x50$Physical address? Base=0x4800, Physical addr = 0x4850, !!Load Byte from 0x4850→$t0, Move PC+4→PC!0x240 main: la $a0, varx 0x244 jal strlen … … 0x360 strlen: li $v0, 0 ;count 0x364 loop: lb $t0, ($a0) 0x368 beq $r0,$t1, done … … 0x4050 varx dw 0x314159 Seg ID #" Base" Limit"0 (code)" 0x4000" 0x0800"1 (data)" 0x4800" 0x1400"2 (shared)" 0xF000" 0x1000"3 (stack)" 0x0000" 0x3000"Lec 9.12!2/16! Ion Stoica CS162 ©UCB Spring 2011!Issues with simple segmentation method"• Fragmentation problem!– Not every process is the same size!– Over time, memory space becomes fragmented!• Hard to do inter-process sharing!– Want to share code segments when possible!– Want to share memory between processes!– Helped by providing multiple segments per process!•
View Full Document
Unlocking...