Page 1 CS162 Operating Systems and Systems Programming Lecture 12 Protection (continued) Address Translation February 25, 2010 Ion Stoica http://inst.eecs.berkeley.edu/~cs162 Lec 12.2 2/25/10 CS162 ©UCB Spring 2010 Review: Important Aspects of Memory Multiplexing • Controlled overlap: – Separate state of threads should not collide in physical memory. Obviously, unexpected overlap causes chaos! – Conversely, would like the ability to overlap when desired (for communication) • Translation: – Ability to translate accesses from one address space (virtual) to a different one (physical) – When translation exists, processor uses virtual addresses, physical memory uses physical addresses – Side effects: » Can be used to avoid overlap » Can be used to give uniform view of memory to programs • Protection: – Prevent access to private memory of other processes » Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc). » Kernel data protected from User programs » Programs protected from themselves Lec 12.3 2/25/10 CS162 ©UCB Spring 2010 Review: General Address Translation Prog 1 Virtual Address Space 1 Prog 2 Virtual Address Space 2 Code Data Heap Stack Code Data Heap Stack Data 2 Stack 1 Heap 1 OS heap & Stacks Code 1 Stack 2 Data 1 Heap 2 Code 2 OS code OS data Translation Map 1 Translation Map 2 Physical Address Space Lec 12.4 2/25/10 CS162 ©UCB Spring 2010 Review: Simple Segmentation: Base and Bounds (CRAY-1) • Can use base & bounds/limit for dynamic address translation (Simple form of “segmentation”): – Alter every address by adding “base” – Generate error if address bigger than limit • This gives program the illusion that it is running on its own dedicated machine, with memory starting at 0 – Program gets continuous region of memory – Addresses within program do not have to be relocated when program placed in different region of DRAM DRAM >? + Base Limit CPU Virtual Address Physical Address Yes: Error!Page 2 Lec 12.5 2/25/10 CS162 ©UCB Spring 2010 Review: Cons for Simple Segmentation Method • Fragmentation problem (complex memory allocation) – Not every process is the same size – Over time, memory space becomes fragmented – Really bad if want space to grow dynamically (e.g. heap) • Other problems for process maintenance – Doesn’t allow heap and stack to grow independently – Want to put these as far apart in virtual memory space as possible so that they can grow as needed • Hard to do inter-process sharing – Want to share code segments when possible – Want to share memory between processes process 6"process 5"process 2"OS"process 6"process 5"OS"process 6"process 5"OS"process 9"process 6"process 5"process 9"OS"process 10"Lec 12.6 2/25/10 CS162 ©UCB Spring 2010 Goals for Today • Address Translation Schemes – Segmentation – Paging – Multi-level translation – Paged page tables – Inverted page tables • Discussion of Dual-Mode operation • Comparison among options Note: Some slides and/or pictures in the following are adapted from slides ©2005 Silberschatz, Galvin, and Gagne Note: Some slides and/or pictures in the following are adapted from slides ©2005 Silberschatz, Galvin, and Gagne. Many slides generated from lecture notes by Kubiatowicz. Lec 12.7 2/25/10 CS162 ©UCB Spring 2010 More Flexible Segmentation • Logical View: multiple separate segments – Typical: Code, Data, Stack – Others: memory sharing, etc • Each segment is given region of contiguous memory – Has a base and limit – Can reside anywhere in physical memory 1"3"2"4"user view of memory space "1"4"2"3"physical memory space 1"2"Lec 12.8 2/25/10 CS162 ©UCB Spring 2010 Implementation of Multi-Segment Model • Segment map resides in processor – Segment number mapped into base/limit pair – Base added to offset to generate physical address – Error check catches offset out of range • As many chunks of physical memory as entries – Segment addressed by portion of virtual address – However, could be included in instruction instead: » x86 Example: mov [es:bx],ax. • What is “V/N”? – Can mark segments as invalid; requires check as well Base0 Limit0 V Base1 Limit1 V Base2 Limit2 V Base3 Limit3 N Base4 Limit4 V Base5 Limit5 N Base6 Limit6 N Base7 Limit7 V Offset Seg # Virtual Address Base2 Limit2 V + Physical Address > ErrorPage 3 Lec 12.9 2/25/10 CS162 ©UCB Spring 2010 Intel x86 Special Registers Typical Segment Register Current Priority is RPL Of Code Segment (CS) 80386 Special Registers Lec 12.10 2/25/10 CS162 ©UCB Spring 2010 Example: Four Segments (16 bit addresses) Seg ID # Base Limit 0 (code) 0x4000 0x0800 1 (data) 0x4800 0x1400 2 (shared) 0xF000 0x1000 3 (stack) 0x0000 0x3000 Offset Seg 0 14 13 15 0x4000 0x0000 0x8000 0xC000 Virtual Address Space Virtual Address Format 0x0000 0x4800 0x5C00 0x4000 0xF000 Physical Address Space Space for Other Apps Shared with Other Apps Might be shared Lec 12.11 2/25/10 CS162 ©UCB Spring 2010 Example of segment translation Let’s simulate a bit of this code to see what happens (PC=0x240): • Fetch 0x240. Virtual segment #? 0; Offset? 0x240 Physical address? Base=0x4000, so physical addr=0x4240 Fetch instruction at 0x4240. Get “la $a0, varx” Move 0x4050 → $a0, Move PC+4→PC 2. Fetch 0x244. Translated to Physical=0x4244. Get “jal strlen” Move 0x0248 → $ra (return address!), Move 0x0360 → PC 3. Fetch 0x360. Translated to Physical=0x4360. Get “li $v0,0” Move 0x0000 → $v0, Move PC+4→PC 4. Fetch 0x364. Translated to Physical=0x4364. Get “lb $t0,($a0)” Since $a0 is 0x4050, try to load byte from 0x4050 Translate 0x4050. Virtual segment #? 1; Offset? 0x50 Physical address? Base=0x4800, Physical addr = 0x4850, Load Byte from 0x4850→$t0, Move PC+4→PC !0x240 main: la $a0, varx 0x244 jal strlen … … 0x360 strlen: li $v0, 0 ;count 0x364 loop: lb $t0, ($a0) 0x368 beq $r0,$t1, done … … 0x4050 varx dw 0x314159 Seg ID # Base Limit 0 (code) 0x4000 0x0800 1 (data) 0x4800 0x1400 2 (shared) 0xF000 0x1000 3 (stack) 0x0000 0x3000 Lec 12.12 2/25/10 CS162 ©UCB Spring 2010 Administrivia • Midterm I coming up in 1 ½ weeks: – Tuesday, 3/9,
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