Review Multi level Translation What about a tree of tables Lowest level page table memory still allocated with bitmap Higher levels often segmented CS162 Operating Systems and Systems Programming Lecture 13 Could have any number of levels Example top segment Virtual Address Caches and TLBs Virtual Seg Base0 Base1 Base2 Base3 Base4 Base5 Base6 Base7 March 12 2008 Prof Anthony D Joseph http inst eecs berkeley edu cs162 Virtual Page Limit0 Limit1 Limit2 Limit3 Limit4 Limit5 Limit6 Limit7 V V V N V N N V Offset page page page page page page 0 V R 1 V R 2 V R W 3 V R W N 4 5 V R W Physical Page Offset Physical Address Check Perm Access Error Access Error What must be saved restored on context switch Contents of top level segment registers for this example Pointer to top level table page table 3 10 08 Review Two level page table 10 bits 10 bits Virtual Virtual Virtual Address P1 index P2 index 12 bits Physical Physical Address Page Pointer to next level page table or to actual page Permission bits valid read only read write write only Offset Example Intel x86 architecture PTE Address same format previous slide 10 10 12 bit offset Intermediate page tables called Directories PageTablePtr Tree of Page Tables Tables fixed size 1024 entries On context switch save single PageTablePtr register 4 bytes Joseph CS162 UCB Spring 2008 3 10 08 Lec 13 3 Page 1 PCD P W U PWT PCD A D L 4 bytes Free 0 L D A UW P OS 11 9 8 7 6 5 4 3 2 1 0 PWT Page Frame Number Physical Page Number 31 12 Sometimes top level page tables called directories Intel Each entry called a surprise Page Table Entry PTE Lec 13 2 Review What is in a PTE What is in a Page Table Entry or PTE Offset 4KB 3 10 08 Joseph CS162 UCB Spring 2008 Present same as valid bit in other architectures Writeable User accessible Page write transparent external cache write through Page cache disabled page cannot be cached Accessed page has been accessed recently Dirty PTE only page has been modified recently L 1 4MB page directory only Bottom 22 bits of virtual address serve as offset Joseph CS162 UCB Spring 2008 Lec 13 4 Goals for Today Caching Concept Caching Translation Look aside Buffers Cache a repository for copies that can be accessed more quickly than the original Make frequent case fast and infrequent case less dominant Caching underlies many of the techniques that are used today to make computers fast Can cache memory locations address translations pages file blocks file names network routes etc Only good if Frequent case frequent enough and Infrequent case not too expensive Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and Gagne 3 10 08 Joseph CS162 UCB Spring 2008 Important measure Average Access time Hit Rate x Hit Time Miss Rate x Miss Time 3 10 08 Lec 13 5 Why Bother with Caching Virtual Address 100 10 1 Less Law Proc 60 yr 2X 1 5yr Processor Memory Performance Gap grows 50 year DRAM DRAM 9 yr 2X 10 yrs Joseph CS162 UCB Spring 2008 Virtual Page Limit0 Limit1 Limit2 Limit3 Limit4 Limit5 Limit6 Limit7 V V V N V N N V Offset page page page page page page 0 V R 1 V R 2 V R W 3 V R W N 4 5 V R W Access Error Physical Page Offset Physical Address Check Perm Access Error Cannot afford to translate on every access At least three DRAM accesses per actual DRAM access Or perhaps I O if page table partially on disk Even worse What if we are using caching to make memory access faster than DRAM access Solution Cache translations Time 3 10 08 Virtual Seg Base0 Base1 Base2 Base3 Base4 Base5 Base6 Base7 CPU 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 Performance Moore s Law really Joy s Law Lec 13 6 Another Major Reason to Deal with Caching Processor DRAM Memory Gap latency 1000 Joseph CS162 UCB Spring 2008 Translation Cache TLB Translation Lookaside Buffer 3 10 08 Lec 13 7 Page 2 Joseph CS162 UCB Spring 2008 Lec 13 8 Why Does Caching Help Locality Administrivia Probability of reference Project 2 code deadline is next Thu 3 20 Having Eclipse startup problems 0 The fix is to delete your eclipse folder rm rf eclipse Then restart eclipse to recreate your config you don t have to delete your workspace 2n 1 Address Space Temporal Locality Locality in Time Keep recently accessed data items closer to processor Please use the CS162 newsgroup for faster response Move contiguous blocks to the upper levels Midterm 2 re grade requests due by Fri 3 14 5pm EECS email is significantly delayed this week Spatial Locality Locality in Space To Processor Talk with us if your grade is 1 2 std devs below mean Lower Level Memory Upper Level Memory Attend a CSUA Unix session to better understand Unix Blk X From Processor 3 10 08 CSUA holds them towards the beginning of each semester Blk Y Joseph CS162 UCB Spring 2008 3 10 08 Lec 13 9 Joseph CS162 UCB Spring 2008 Lec 13 10 Jim Gray s Storage Latency Analogy How Far Away is the Data Memory Hierarchy of a Modern Computer System Take advantage of the principle of locality to Present as much memory as in the cheapest technology Provide access at speed offered by the fastest technology 109 10 6 Disk Processor Control 1s Size bytes 100s 3 10 08 On Chip Cache Speed ns Registers Datapath Andromeda Tape Optical Robot Second Level Cache SRAM 10s 100s Ks Ms Main Memory DRAM 100s Ms Gs Joseph CS162 UCB Spring 2008 Secondary Storage Disk 10 2 1 10 000 000s 10 000 000 000s 10s ms 10s sec Gs Ts Pluto Tertiary Storage Tape 100 2 000 Years Sacramento Memory On Board Cache On Chip Cache Registers 2 Years 1 5 hr This Lecture Hall 10 min This Room My Head 1 min Ts Ps 3 10 08 Lec 13 11 Page 3 Joseph CS162 UCB Spring 2008 Lec 13 12 A Summary on Sources of Cache Misses How is a Block found in a Cache Compulsory cold start or process migration first reference first access to a block Block Address Cold fact of life not a whole lot you can do about it Note If you are going to run billions of instruction Compulsory Misses are insignificant Set Select Capacity Cache cannot contain all blocks access by the program Solution increase cache size Data Select Index Used to Lookup Candidates in Cache Index identifies the set Conflict collision Tag used to identify actual copy Multiple memory locations mapped to the same cache location Solution 1 increase cache size Solution 2 increase associativity If no candidates match then declare cache miss Block is minimum quantum of caching Data select field used to select data within …
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