Page 1CS162Operating Systems andSystems ProgrammingLecture 13Caches and TLBsMarch 12, 2008Prof. Anthony D. Josephhttp://inst.eecs.berkeley.edu/~cs162Lec 13.23/10/08 Joseph CS162 ©UCB Spring 2008• What about a tree of tables?– Lowest level page tablememory still allocated with bitmap– Higher levels often segmented• Could have any number of levels. Example (top segment):• What must be saved/restored on context switch?– Contents of top-level segment registers (for this example)– Pointer to top-level table (page table)Review: Multi-level Translationpage #0page #1page #3page #4page #5V,RV,Rpage #2V,R,WV,R,WNV,R,WOffsetPhysical AddressVirtual Address:OffsetVirtualPage #VirtualSeg #Base0 Limit0 VBase1 Limit1 VBase2 Limit2 VBase3 Limit3 NBase4 Limit4 VBase5 Limit5 NBase6 Limit6 NBase7 Limit7 VBase2 Limit2 VAccessError>page #2V,R,WPhysicalPage #Check PermAccessErrorLec 13.33/10/08 Joseph CS162 ©UCB Spring 2008PhysicalAddress:OffsetPhysicalPage #4KBReview: Two-level page table10 bits 10 bits 12 bitsVirtual Address:OffsetVirtualP2 indexVirtualP1 index4 bytesPageTablePtr• Tree of Page Tables• Tables fixed size (1024 entries)– On context-switch: save single PageTablePtr register• Sometimes, top-level page tables called “directories” (Intel)• Each entry called a (surprise!) Page Table Entry (PTE)4 bytesLec 13.43/10/08 Joseph CS162 ©UCB Spring 2008Review: What is in a PTE?• What is in a Page Table Entry (or PTE)?– Pointer to next-level page table or to actual page– Permission bits: valid, read-only, read-write, write-only• Example: Intel x86 architecture PTE:– Address same format previous slide (10, 10, 12-bit offset)– Intermediate page tables called “Directories”P: Present (same as “valid” bit in other architectures) W: WriteableU: User accessiblePWT: Page write transparent: external cache write-throughPCD: Page cache disabled (page cannot be cached)A: Accessed: page has been accessed recentlyD: Dirty (PTE only): page has been modified recentlyL: L=14MB page (directory only).Bottom 22 bits of virtual address serve as offsetPage Frame Number(Physical Page Number)Free(OS)0 L D APCDPWTU W P01234567811-931-12Page 2Lec 13.53/10/08 Joseph CS162 ©UCB Spring 2008Goals for Today• Caching• Translation Look-aside BuffersNote: Some slides and/or pictures in the following areadapted from slides ©2005 Silberschatz, Galvin, and Gagne Lec 13.63/10/08 Joseph CS162 ©UCB Spring 2008Caching Concept• Cache: a repository for copies that can be accessed more quickly than the original– Make frequent case fast and infrequent case less dominant• Caching underlies many of the techniques that are used today to make computers fast– Can cache: memory locations, address translations, pages, file blocks, file names, network routes, etc…• Only good if:– Frequent case frequent enough and– Infrequent case not too expensive• Important measure: Average Access time = (Hit Rate x Hit Time) + (Miss Rate x Miss Time)Lec 13.73/10/08 Joseph CS162 ©UCB Spring 2008CPUµProc60%/yr.(2X/1.5yr)DRAM9%/yr.(2X/10 yrs)DRAM1101001000198019811983198419851986198719881989199019911992199319941995199619971998199920001982Processor-MemoryPerformance Gap:(grows 50% / year)PerformanceTime“Moore’s Law”(really Joy’s Law)Processor-DRAM Memory Gap (latency)Why Bother with Caching?“Less’ Law?”Lec 13.83/10/08 Joseph CS162 ©UCB Spring 2008• Cannot afford to translate on every access– At least three DRAM accesses per actual DRAM access– Or: perhaps I/O if page table partially on disk!• Even worse: What if we are using caching to make memory access faster than DRAM access???• Solution? Cache translations!– Translation Cache: TLB (“Translation Lookaside Buffer”)Another Major Reason to Deal with Cachingpage #0page #1page #3page #4page #5V,RV,Rpage #2V,R,WV,R,WNV,R,WOffsetPhysical AddressVirtual Address:OffsetVirtualPage #VirtualSeg #Base0 Limit0 VBase1 Limit1 VBase2 Limit2 VBase3 Limit3 NBase4 Limit4 VBase5 Limit5 NBase6 Limit6 NBase7 Limit7 VAccessError>PhysicalPage #Check PermAccessErrorPage 3Lec 13.93/10/08 Joseph CS162 ©UCB Spring 2008Why Does Caching Help? Locality!• Temporal Locality (Locality in Time):– Keep recently accessed data items closer to processor• Spatial Locality (Locality in Space):– Move contiguous blocks to the upper levels Address Space0 2n- 1Probabilityof referenceLower LevelMemoryUpper LevelMemoryTo ProcessorFrom ProcessorBlk XBlk YLec 13.103/10/08 Joseph CS162 ©UCB Spring 2008Administrivia• Project #2 code deadline is next Thu (3/20)– Having Eclipse startup problems?» The fix is to delete your ~/.eclipse folder:rm -rf ~/.eclipseThen restart eclipse to recreate your config, you don’t have to delete your workspace• Please use the CS162 newsgroup for faster response– EECS email is significantly delayed this week• Midterm #2 re-grade requests due by Fri 3/14 5pm– Talk with us if your grade is 1-2 std devs below mean• Attend a CSUA Unix session to better understand Unix– CSUA holds them towards the beginning of each semesterLec 13.113/10/08 Joseph CS162 ©UCB Spring 2008Memory Hierarchy of a Modern Computer System• Take advantage of the principle of locality to:– Present as much memory as in the cheapest technology– Provide access at speed offered by the fastest technologyOn-ChipCacheRegistersControlDatapathSecondaryStorage(Disk)ProcessorMainMemory(DRAM)SecondLevelCache(SRAM)1s10,000,000s (10s ms)Speed (ns): 10s-100s 100s100s Gs-TsSize (bytes): Ks-Ms Ms-GsTertiaryStorage(Tape)10,000,000,000s (10s sec)Ts-PsLec 13.123/10/08 Joseph CS162 ©UCB Spring 2008Jim Gray’s Storage Latency Analogy: How Far Away is the Data?RegistersOn Chip CacheOn Board CacheMemory Disk1210100Tape /Optical Robot109106SacramentoThis Lecture HallThis RoomMy Head10 min1.5 hr2 Years1 minPluto2,000 YearsAndromedaPage 4Lec 13.133/10/08 Joseph CS162 ©UCB Spring 2008• Compulsory (cold start or process migration, first reference): first access to a block– “Cold” fact of life: not a whole lot you can do about it– Note: If you are going to run “billions” of instruction, Compulsory Misses are insignificant• Capacity:– Cache cannot contain all blocks access by the program– Solution: increase cache size• Conflict (collision):– Multiple memory locations mappedto the same cache location– Solution 1: increase cache size– Solution 2: increase associativity• Coherence (Invalidation): other process
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