CS162 Operating Systems and Systems Programming Lecture 12 Protection continued Address Translation October 10 2005 Prof John Kubiatowicz http inst eecs berkeley edu cs162 Review Multi Level Feedback Scheduling Long Running Comput Tasks Demoted to Low Priority Another method for exploiting past behavior First used in CTSS Multiple queues each with different priority Higher priority queues often considered foreground tasks Each queue has its own scheduling algorithm e g foreground RR background FCFS Sometimes multiple RR priorities with quantum increasing exponentially highest 1ms next 2ms next 4ms etc Adjust each job s priority as follows details vary Job starts in highest priority queue If timeout expires drop one level If timeout doesn t expire push up one level or to top 10 10 05 Kubiatowicz CS162 UCB Fall 2005 Lec 12 2 Review Lottery Scheduling Example Lottery Scheduling Example Assume short jobs get 10 tickets long jobs get 1 ticket of CPU each short jobs of CPU each short jobs long jobs gets long jobs gets 1 1 91 9 0 2 N A 50 2 0 50 N A 10 1 9 9 0 99 1 10 50 5 What if too many short jobs to give reasonable response time In UNIX if load average is 100 hard to make progress One approach log some user out 10 10 05 Kubiatowicz CS162 UCB Fall 2005 Lec 12 3 Review Important Aspects of Memory Multiplexing Controlled overlap Separate state of threads should not collide in physical memory Obviously unexpected overlap causes chaos Conversely would like the ability to overlap when desired for communication Translation Ability to translate accesses from one address space virtual to a different one physical When translation exists processor uses virtual addresses physical memory uses physical addresses Side effects Can be used to avoid overlap Can be used to give uniform view of memory to programs Protection Prevent access to private memory of other processes Different pages of memory can be given special behavior Read Only Invisible to user programs etc Kernel data protected from User programs Programs protected from themselves 10 10 05 Kubiatowicz CS162 UCB Fall 2005 Lec 12 4 Goals for Today Finish discussion of protection Address Translation Schemes Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and 10 10 05 Kubiatowicz CS162 UCB Fall 2005 Lec 12 5 Gagne Dual Mode Operation To Assist with Protection Hardware provides at least two modes Dual Mode Operation Kernel mode or supervisor or protected User mode Normal program mode Mode set with bits in special control register only accessible in kernel mode Intel processor actually has four rings of protection PL Priviledge Level from 0 3 PL0 has full access PL3 has least Privilege Level set in code segment descriptor CS Mirrored IOPL bits in condition register gives permission to programs to use the I O instructions Typical OS kernels on Intel processors only use PL0 user and PL3 kernel 10 10 05 Kubiatowicz CS162 UCB Fall 2005 Lec 12 6 For Protection Lock User Programs in Asylum Idea Lock user programs in padded cell with no exit or sharp objects Cannot change mode to kernel mode User cannot modify page table mapping Limited access to memory cannot adversely effect other processes Side effect Limited access to memory mapped I O operations I O that occurs by reading writing memory locations Limited access to interrupt controller What else needs to be protected A couple of issues How to share CPU between kernel and user programs Kinda like both the inmates and the warden in asylum are the same person How do you manage this How do programs interact How does one switch between kernel and user modes 10 10 05 OS user kernel user mode getting into cell User OS user kernel mode getting out of cell Kubiatowicz CS162 UCB Fall 2005 Lec 12 7 How to get from Kernel User What does the kernel do to create a new user process Allocate and initialize address space control block Read program off disk and store in memory Allocate and initialize translation table Point at code in memory so program can execute Possibly point at statically initialized data Run Program Set machine registers Set hardware pointer to translation table Set processor status word for user mode Jump to start of program How does kernel switch between processes Same saving restoring of registers as before Save restore hardware pointer to translation table 10 10 05 Kubiatowicz CS162 UCB Fall 2005 Lec 12 8 User Kernel System Call Can t let inmate user get out of padded cell on own Would defeat purpose of protection So how does the user program get back into kernel System call Voluntary procedure call into kernel Hardware for controlled User Kernel transition Can any kernel routine be called No Only specific ones System call ID encoded into system call instruction 10 10 05 Index forces well defined interface with kernel Kubiatowicz CS162 UCB Fall 2005 Lec 12 9 System Call Continued What are some system calls I O open close read write lseek Files delete mkdir rmdir truncate chown chgrp Process fork exit wait like join Network socket create set options Are system calls constant across operating systems Not entirely but there are lots of commonalities Also some standardization attempts POSIX What happens at beginning of system call Hardware entry to kernel sets system to kernel mode Handler address fetched from table Handler started System Call argument passing In registers not very much can be passed Write into user memory kernel copies into kernel mem User addresses must be translated w Kernel has different view of memory than user Every 10 10 05 Argument must be UCB explicitly checked Kubiatowicz CS162 Fall 2005 Lec 12 10 User Kernel Exceptions Traps and Interrupts A system call instruction causes a synchronous exception or trap In fact often called a software trap instruction Other sources of synchronous exceptions Divide by zero Illegal instruction Bus error bad address e g unaligned access Segmentation Fault address out of range Page Fault for illusion of infinite sized memory Interrupts are Asynchronous Exceptions Examples timer disk ready network etc Interrupts can be disabled traps cannot On system call exception or interrupt Hardware enters kernel mode with interrupts disabled Saves PC then jumps to appropriate handler in kernel For some processors x86 processor also saves registers changes stack etc Actual handler typically saves registers other CPU state and switches to kernel 10 10 05 Kubiatowicz CS162 UCB stack Fall 2005 Lec 12
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