Review Memory Hierarchy of a Modern Computer System Take advantage of the principle of locality to CS162 Operating Systems and Systems Programming Lecture 14 Present as much memory as in the cheapest technology Provide access at speed offered by the fastest technology Processor Caching and Demand Paging Control Speed ns On Chip Cache Datapath Registers October 19 2005 Prof John Kubiatowicz http inst eecs berkeley edu cs162 1s Size bytes 100s 10 19 05 Review A Summary on Sources of Cache Misses Compulsory cold start or process migration first reference first access to a block Second Level Cache SRAM Secondary Storage Disk Main Memory DRAM 10s 100s 100s Ks Ms Ms Tertiary Storage Tape 10 000 000s 10 000 000 000s 10s ms 10s sec Gs Kubiatowicz CS162 UCB Fall 2005 Ts Lec 14 2 Review Where does a Block Get Placed in a Cache Example Block 12 placed in 8 block cache 32 Block Address Space Cold fact of life not a whole lot you can do about it Note If you are going to run billions of instruction Compulsory Misses are insignificant Capacity Block no Cache cannot contain all blocks access by the program Solution increase cache size Conflict collision Multiple memory locations mapped to the same cache location Solution 1 increase cache size Solution 2 increase associativity 10 19 05 Kubiatowicz CS162 UCB Fall 2005 Direct mapped Set associative Fully associative block 12 can go only into block 4 12 mod 8 block 12 can go anywhere in set 0 12 mod 4 block 12 can go anywhere Block no Coherence Invalidation other process e g I O updates memory Lec 14 3 1111111111222222222233 01234567890123456789012345678901 10 19 05 01234567 Block no 01234567 Block no Set Set Set Set 0 1 2 3 Kubiatowicz CS162 UCB Fall 2005 01234567 Lec 14 4 Review Other Caching Questions Goals for Today What line gets replaced on cache miss Easy for Direct Mapped Only one possibility Set Associative or Fully Associative Random LRU Least Recently Used What happens on a write Finish discussion of TLBs Concept of Paging to Disk Page Faults and TLB Faults Precise Interrupts Page Replacement Policies Write through The information is written to both the cache and to the block in the lower level memory Write back The information is written only to the block in the cache Modified cache block is written to main memory only when it is replaced Question is block clean or dirty 10 19 05 Kubiatowicz CS162 UCB Fall 2005 Lec 14 5 Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and Gagne 10 19 05 Kubiatowicz CS162 UCB Fall 2005 Lec 14 6 Caching Applied to Address Translation Quick Aside Protection without Hardware Does protection require hardware support for translation and dual mode behavior No Normally use hardware but anything you can do in hardware can also do in software possibly expensive CPU Protection via Strong Typing Restrict programming language so that you can t express program that would trash another program Loader needs to make sure that program produced by valid compiler or all bets are off Example languages LISP Ada Modula 3 and Java Protection via software fault isolation Virtual Address TLB Cached Yes No Translate MMU Physical Address ve t Sa sul Re Physical Memory Data Read or Write untranslated Language independent approach have compiler generate object code that provably can t step out of bounds Question is one of page locality does it exist Or use virtual machine to guarantee safe behavior loads and stores recompiled on fly to check bounds Can we have a TLB hierarchy Compiler puts in checks for every dangerous operation loads stores etc Again need special loader Alternative compiler generates proof that code cannot do certain things Proof Carrying Code 10 19 05 Kubiatowicz CS162 UCB Fall 2005 Lec 14 7 Instruction accesses spend a lot of time on the same page since accesses sequential Stack accesses have definite locality of reference Data accesses have less page locality but still some Sure multiple levels at different sizes speeds 10 19 05 Kubiatowicz CS162 UCB Fall 2005 Lec 14 8 TLB organization Example R3000 pipeline includes TLB stages How big does TLB actually have to be Usually small 128 512 entries Not very big can support higher associativity MIPS R3000 Pipeline TLB usually organized as fully associative cache What happens when fully associative is too slow Put a small 4 16 entry direct mapped cache in front Called a TLB Slice 10 19 05 N Y Y Y Y Y Kubiatowicz CS162 UCB Fall 2005 R W R R Lec 14 9 As described TLB lookup is in serial with cache lookup ASID 6 V Page Number 20 Access Rights 10 19 05 index TLB Hit Miss FN 4K Cache 10 2 disp 00 20 page Physical Address Machines with TLBs go one step further they overlap TLB lookup with cache access Works because offset available early Lec 14 11 1 K 4 bytes FN Data What if cache size is increased to 8KB offset 10 Kubiatowicz CS162 UCB Fall 2005 Lec 14 10 Overlapping TLB Cache Access Here is how this might work with a 4K cache 32 PA D Cache Offset 12 assoc lookup P page no 10 19 05 TLB WB Allows context switching among 64 user processes without TLB flush Kubiatowicz CS162 UCB Fall 2005 TLB Lookup V Write Reg 0xx User segment caching based on PT TLB entry 100 Kernel physical space cached 101 Kernel physical space uncached 11x Kernel virtual space Virtual Address 10 offset Memory Operation Virtual Address Space 34 0 0 Reducing translation time further V page no ALU E A 64 entry on chip fully associative software TLB fault handler Virtual Address Physical Address Dirty Ref Valid Access ASID Y N N RF TLB Example for MIPS R3000 0x0003 0x0010 0x0011 I Cache E A Lookup is by Virtual Address Returns Physical Address other info 0xFA00 0x0040 0x0041 Dcd Reg Inst Fetch TLB Hit Miss Overlap not complete Need to do something else See CS152 252 Another option Virtual Caches Tags in cache are virtual addresses Translation only happens on cache misses 10 19 05 Kubiatowicz CS162 UCB Fall 2005 Lec 14 12 Administrivia Demand Paging Exam is graded grades should be in glookup Modern programs require a lot of physical memory Average 71 2 Standard Dev 12 3 Min 23 Max 96 But they don t use all their memory all of the time There will be a lot of information about the projects that I cannot cover in class Also supplemental information and detail that we don t have time for in class Solution use main memory as cache for disk Memory per system growing faster than 25 30 year Make sure to come to sections One more comment on Problem 3 and multithreading
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