CS162 Operating Systems and Systems Programming Lecture 15 Page Allocation and Replacement March 11 2010 Ion Stoica http inst eecs berkeley edu cs162 Review Paging Address Translation Physical Memory Virtual Address Virtual Virtual Offset P1 indexP2 index PageTablePtr Physical Address Physical Offset Page Page Table 1st level Page Table 2nd level 3 11 10 CS162 UCB Spring 2010 Lec 15 2 Review Translation Look aside Buffer Physical Memory Virtual Address Virtual Virtual Offset P1 indexP2 index PageTablePtr Physical Address Physical Offset Page Page Table 1st level TLB Page Table 2nd level 3 11 10 CS162 UCB Spring 2010 Lec 15 3 Review Cache Physical Memory Virtual Address Virtual Virtual Offset P1 indexP2 index PageTablePtr Physical Address Physical Offset Page Page Table 1st level TLB tag Page Table 2nd level index byte cache tag 3 11 10 bloc k CS162 UCB Spring 2010 Lec 15 4 Review Demand Paging Mechanisms PTE helps us implement demand paging Valid Page in memory PTE points at physical page Not Valid Page not in memory use info in PTE to find it on disk when necessary Suppose user references page with invalid PTE Memory Management Unit MMU traps to OS Resulting trap is a Page Fault What does OS do on a Page Fault Choose an old page to replace If old page modified D 1 write contents back to disk Change its PTE and any cached TLB to be invalid Load new page into memory from disk Update page table entry invalidate TLB for new entry Continue thread from original faulting location TLB for new page will be loaded when thread continued While pulling pages off disk for one process OS runs another process from ready queue 3 11 10 Suspended process on wait2010 queue CS162sits UCB Spring Lec 15 5 Goals for Today Precise Exceptions Page Replacement Policies Clock Algorithm Nth chance algorithm Second Chance List Algorithm Page Allocation Policies Working Set Thrashing Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and 3 11 10 UCB Spring 2010 Lec 15 6 Gagne Many slidesCS162 Gagne generated from my lecture notes OS Load TLB Faulting Inst 2 Faulting Inst 2 TLB Faults Faulting Inst 1 User Faulting Inst 1 Transparent Exceptions Fetch page Load TLB How to transparently restart faulting instructions Could we just skip it No need to perform load or store after reconnecting physical page Hardware must help out by saving Faulting instruction and partial state Need to know which instruction caused fault Is single PC sufficient to identify faulting position Processor State sufficient to restart user thread Save restore registers stack etc What if an instruction has side effects 3 11 10 CS162 UCB Spring 2010 Lec 15 7 Consider weird things that can happen What if an instruction has side effects Options Unwind side effects easy to restart Finish off side effects messy Example 1 mov sp 10 What if page fault occurs when write to stack pointer Did sp get incremented before or after the page fault Example 2 strcpy r1 r2 Source and destination overlap can t unwind in principle IBM S 370 and VAX solution execute twice once readonly What about RISC processors For instance delayed branches Example bne somewhere ld r1 sp Precise exception state consists of two PCs PC and nPC Delayed exceptions 3 11 10 Example div r1 r2 r3 ld r1 sp What if takes many cycles to discover divide by zero but load has already caused page fault CS162 UCB Spring 2010 Lec 15 8 Precise Exceptions Precise state of the machine is preserved as if program executed up to the offending instruction All previous instructions completed Offending instruction and all following instructions act as if they have not even started Same system code will work on different implementations Difficult in the presence of pipelining out of order execution MIPS takes this position Imprecise system software has to figure out what is where and put it all back together Performance goals often lead designers to forsake precise interrupts system software developers user markets etc usually wish they had not done this Modern techniques for out of order execution 3 11 10 CS162 UCB Spring 2010 Lec 15 9 and branch prediction help implement precise Steps in Handling a Page Fault 3 11 10 CS162 UCB Spring 2010 Lec 15 10 Demand Paging Example Since Demand Paging like caching can compute average access time Effective Access Time EAT Hit Rate x Hit Time Miss Rate x Miss Time Example Memory access time 200 nanoseconds Average page fault service time 8 milliseconds Suppose p Probability of miss 1 p Probably of hit Then we can compute EAT as follows EAT 1 p x 200ns p x 8 ms 1 p x 200ns p x 8 000 000ns 200ns p x 7 999 800ns If one access out of 1 000 causes a page fault then EAT 8 2 s This is a slowdown by a factor of 40 What if want slowdown by less than 10 200ns x 1 1 EAT p 2 5 x 10 6 This is about 1 page fault in 400 000 3 11 10 CS162 UCB Spring 2010 Lec 15 11 What Factors Lead to Misses Compulsory Misses Pages that have never been paged into memory before How might we remove these misses Prefetching loading them into memory before needed Need to predict future somehow More later Capacity Misses Not enough memory Must somehow increase size Can we do this One option Increase amount of DRAM not quick fix Another option If multiple processes in memory adjust percentage of memory allocated to each one Conflict Misses Technically conflict misses don t exist in virtual memory since it is a fully associative cache Policy Misses Caused when pages were in memory but kicked out prematurely because of the replacement policy How to fix Better replacement policy 3 11 10 CS162 UCB Spring 2010 Lec 15 12 Administrivia Midterm exam statistics Mean score 80 4 Median score 82 5 Standard Dev 11 1 Max 101 By tomorrow Solutions will be up Grades in glookup Regrading policy you have one week until 3 18 One page explaining Which problem you want to be regraded and why look at solution first We will regrade your entire exam so there is a chance your grade may decrease All in all Excellent grades Congratulations 3 11 10 CS162 UCB Spring 2010 Lec 15 13 Page Replacement Policies Why do we care about Replacement Policy Replacement is an issue with any cache Particularly important with pages The cost of being wrong is high must go to disk Must keep important pages in memory not toss them out FIFO First In First Out Throw out oldest page Be fair let every page live in memory for same amount of time Bad because throws out heavily used pages instead of
View Full Document
Unlocking...