CS162 Operating Systems and Systems Programming Lecture 9 Address TranslationReview: Important Aspects of Memory MultiplexingGoals for TodayUniprograming: Loading Program in MemoryMultiprograming: Where do you load program?Example of General Address TranslationSegmentation with Base and Limit RegistersMore Flexible SegmentationImplementation of Multi-Segment ModelExample: Four Segments (16 bit addresses)Example of segment translationIssues with simple segmentation methodObservations about SegmentationSchematic View of SwappingPaging: Physical Memory in Fixed Size ChunksHow to Implement Paging?What about Sharing?Simple Page Table DiscussionMulti-level TranslationWhat about Sharing (Complete Segment)?5min BreakAnother common example: two-level page tableMulti-level Translation AnalysisInverted Page TableDual-Mode OperationFor Protection, Lock User-Programs in AsylumHow to get from KernelUserUserKernel (System Call)System Call ContinuedUserKernel (Exceptions: Traps and Interrupts)Closing thought: Protection without HardwareSummary (1/2)Summary (2/2)CS162Operating Systems andSystems ProgrammingLecture 9Address TranslationFebruary 16, 2011Ion Stoicahttp://inst.eecs.berkeley.edu/~cs162Lec 9.22/16 Ion Stoica CS162 ©UCB Spring 2011Review: Important Aspects of Memory Multiplexing•Controlled overlap:–Ability to explicitly control whether to processes should share or not a region of memory•Protection:–Prevent access to private memory of other processes»Kernel data protected from User programs»Programs protected from themselves»Different pages of memory can be given special behavior (Read Only, Invisible to user programs, etc)•Translation: –Ability to translate accesses from one address space (virtual) to a different one (physical)–When translation exists, processor uses virtual addresses, physical memory uses physical addresses–Side effects:»Can be used to avoid overlap»Can be used to give uniform view of memory to programsLec 9.32/16 Ion Stoica CS162 ©UCB Spring 2011Goals for Today•Address Translation Schemes–Segmentation–Paging–Multi-level translation–Paged page tables–Inverted page tables•Discussion of Dual-Mode operationNote: Some slides and/or pictures in the following are adapted from slides ©2005 Silberschatz, Galvin, and Gagne. Many slides generated from lecture notes by Kubiatowicz.Lec 9.42/16 Ion Stoica CS162 ©UCB Spring 2011Uniprograming: Loading Program in Memory0x300 00000020 … …0x900 8C2000C00x904 0C0003400x908 2021FFFF0x90C 1420FFFF …8C2000C00C0003402021FFFF1420FFFF0x09000xFFFF0x03000x000000000020data1: dw 32…start: lw r1,0(data1)jal checkitloop: addi r1, r1, -1bnz r1, r0, loop…checkit: …Program view of memoryMemoryLec 9.52/16 Ion Stoica CS162 ©UCB Spring 2011Multiprograming: Where do you load program?0x300 00000020 … …0x900 8C2000C00x904 0C0003400x908 2021FFFF0x90C 1420FFFF …0x09000xFFFF0x03000x0000data1: dw 32…start: lw r1,0(data1)jal checkitloop: addi r1, r1, -1bnz r1, r0, loop…checkit: …Program view of memoryMemoryApp X?Need address translation!Lec 9.62/16 Ion Stoica CS162 ©UCB Spring 2011Example of General Address TranslationProg 1VirtualAddressSpace 1Prog 2VirtualAddressSpace 2CodeDataHeapStackCodeDataHeapStackData 2Stack 1Heap 1OS heap & StacksCode 1Stack 2Data 1Heap 2Code 2OS codeOS dataTranslation Map 1 Translation Map 2Physical Address SpaceLec 9.72/16 Ion Stoica CS162 ©UCB Spring 2011Segmentation with Base and Limit Registers•Could use base/limit for dynamic address translation (often called “segmentation”):–Alter address of every load/store by adding “base”–User allowed to read/write within segment»Accesses are relative to segment so don’t have to be relocated when program moved to different segment–User may have multiple segments available (e.g x86)»Loads and stores include segment ID in opcode:x86 Example: mov [es:bx],ax. »Operating system moves around segment base pointers as necessaryDRAM<?+BaseLimitCPUVirtualAddressPhysicalAddressNo: Error!Lec 9.82/16 Ion Stoica CS162 ©UCB Spring 2011More Flexible Segmentation•Logical View: multiple separate segments–Typical: Code, Data, Stack–Others: memory sharing, etc•Each segment is given region of contiguous memory–Has a base and limit–Can reside anywhere in physical memory1324user view ofmemory space 1423physical memory space12Lec 9.92/16 Ion Stoica CS162 ©UCB Spring 2011Implementation of Multi-Segment Model•Segment map resides in processor–Segment number mapped into base/limit pair–Base added to offset to generate physical address–Error check catches offset out of range•As many chunks of physical memory as entries–Segment addressed by portion of virtual address–However, could be included in instruction instead:»x86 Example: mov [es:bx],ax. •What is “V/N”?–Can mark segments as invalid; requires check as wellBase0 Limit0 VBase1 Limit1 VBase2 Limit2 VBase3 Limit3 NBase4 Limit4 VBase5 Limit5 NBase6 Limit6 NBase7 Limit7 VOffsetSeg #VirtualAddressBase2 Limit2 V+PhysicalAddress>ErrorLec 9.102/16 Ion Stoica CS162 ©UCB Spring 2011Example: Four Segments (16 bit addresses)Seg ID # Base Limit0 (code) 0x4000 0x08001 (data) 0x4800 0x14002 (shared) 0xF000 0x10003 (stack) 0x0000 0x3000OffsetSeg014 13150x40000x00000x80000xC000VirtualAddress SpaceVirtual Address Format0x00000x48000x5C000x40000xF000PhysicalAddress SpaceSpace forOther AppsShared withOther AppsMight be sharedLec 9.112/16 Ion Stoica CS162 ©UCB Spring 2011Example of segment translationLet’s simulate a bit of this code to see what happens (PC=0x240):1. Fetch 0x240. Virtual segment #? 0; Offset? 0x240Physical address? Base=0x4000, so physical addr=0x4240Fetch instruction at 0x4240. Get “la $a0, varx”Move 0x4050 $a0, Move PC+4PC2. Fetch 0x244. Translated to Physical=0x4244. Get “jal strlen”Move 0x0248 $ra (return address!), Move 0x0360 PC3. Fetch 0x360. Translated to Physical=0x4360. Get “li $v0,0”Move 0x0000 $v0, Move PC+4PC4. Fetch 0x364. Translated to Physical=0x4364. Get “lb $t0,($a0)”Since $a0 is 0x4050, try to load byte from 0x4050Translate 0x4050. Virtual segment #? 1; Offset? 0x50Physical address? Base=0x4800, Physical addr = 0x4850, Load Byte from 0x4850$t0, Move PC+4PC0x240 main: la $a0, varx0x244 jal strlen … …0x360 strlen: li $v0, 0 ;count0x364 loop: lb $t0, ($a0)0x368 beq $r0,$t1, done … …0x4050 varx dw 0x314159Seg ID # Base Limit0 (code) 0x4000
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