Who am I CS162 Operating Systems and Systems Programming Lecture 1 Ion Stoica Research Networking Topics Quality of service architectures Projects Internet Indirection Infrastructure Declarative Networks Peer to Peer What is an Operating System Topics distributed hash tables lookup services Projects Chord Internet Indirection Infrastructure Cloud computing January 19th 2010 Ion Stoica http inst eecs berkeley edu cs162 Topics Scheduling resource management Projects Nexus Cloud OS Spark Debugging and Replaying Projects Liblog Friday ODR Output Deterministic Replay 1 19 10 Goals for Today Ion Stoica CS162 UCB Spring 2010 Lec 1 2 Technology Trends Moore s Law What is an Operating System And what is it not Examples of Operating Systems design Why study Operating Systems Oh and How does this class operate Moore s Law Interactive is important Ask Questions 2X transistors Chip Every 1 5 years Gordon Moore co founder of Intel predicted in 1965 that the transistor density of semiconductor chips would double roughly every 18 months Note Some slides and or pictures in the following are adapted from slides 2005 Silberschatz Galvin and Gagne Slides courtesy of Kubiatowicz AJ Shankar George Necula Alex Aiken Eric Brewer Ras Bodik Ion Stoica Doug Tygar and David Wagner 1 19 10 Ion Stoica CS162 UCB Spring 2010 1 19 10 Lec 1 3 Page 1 Called Moore s Law Microprocessors have become smaller denser and more powerful Ion Stoica CS162 UCB Spring 2010 Lec 1 4 Societal Scale Information Systems People to Computer Ratio Over Time The world is a large parallel system Microprocessors in everything Vast infrastructure behind them From David Culler Massive Cluster Gigabit Ethernet Internet Connectivity Clusters Scalable Reliable Secure Services Databases Information Collection Remote Storage Online Games Commerce MEMS for Sensor 1 19 10 Nets Today Multiple CPUs person Ion Stoica CS162 UCB Spring 2010 1 19 10 Lec 1 5 Lec 1 6 Intel 80 core multicore chip Feb 2007 3X 80 simple cores Two floating point engines core Mesh like network on a chip 100 million transistors 65nm feature size Frequency Voltage Power Bandwidth Performance 3 16 GHz 0 95 V 62W 1 62 Terabits s 1 01 Teraflops 5 1 GHz 1 2 V 175W 2 61 Terabits s 1 63 Teraflops 5 7 GHz 1 35 V 265W 2 92 Terabits s 1 81 Teraflops Sea change in chip design multiple cores or processors per chip VAX 25 year 1978 to 1986 RISC x86 52 year 1986 to 2002 RISC x86 year Ion 2002 to CS162 present 1 19 10 Stoica UCB Ion Stoica CS162 UCB Spring 2010 ManyCore Chips The future is here New Challenge Slowdown in Joy s law of Performance From Hennessy and Patterson Computer Architecture A Quantitative Approach 4th edition Sept 15 2006 Approaching 100s ManyCore refers to many processors chip 64 128 Hard to say exact boundary How to program these Use 2 CPUs for video audio Use 1 for word processor 1 for browser 76 for virus checking Spring 2010 Parallelism must Ion beStoica exploited at all levels CS162 UCB Spring 2010 1 19 10 Lec 1 7 Page 2 Lec 1 8 Another Challenge Power Density Computer System Organization Computer system operation One or more CPUs device controllers connect through common bus providing access to shared memory Concurrent execution of CPUs and devices competing for memory cycles Moore s Law Extrapolation Potential power density reaching amazing levels Flip side Battery life very important Moore s law can yield more functionality at equivalent or less total energy consumption 1 19 10 Ion Stoica CS162 UCB Spring 2010 1 19 10 Lec 1 9 Sample of Computer Architecture Topics Ion Stoica CS162 UCB Spring 2010 Lec 1 10 Increasing Software Complexity Input Output and Storage Disks WORM Tape VLSI Coherence Bandwidth Latency L2 Cache L1 Cache Instruction Set Architecture Addressing Protection Exception Handling Pipelining Hazard Resolution Superscalar Reordering Prediction Speculation Vector Dynamic Compilation 1 19 10 Network Communication Other Processors Emerging Technologies Interleaving Bus protocols DRAM Memory Hierarchy RAID Pipelining and Instruction Level Parallelism Ion Stoica CS162 UCB Spring 2010 From MIT s 6 033 course 1 19 10 Lec 1 11 Page 3 Ion Stoica CS162 UCB Spring 2010 Lec 1 12 Example Some Mars Rover Pathfinder Requirements How do we tame complexity Pathfinder hardware limitations complexity 20Mhz processor 128MB of DRAM VxWorks OS cameras scientific instruments batteries solar panels and locomotion equipment Many independent processes work together Can t hit reset button very easily Must reboot itself if necessary Must always be able to receive commands from Earth Individual Programs must not interfere Suppose the MUT Martian Universal Translator Module buggy Better not crash antenna positioning software Further all software may crash occasionally Automatic restart with diagnostics sent to Earth Periodic checkpoint of results saved Certain functions time critical Need to stop before hitting something Must track orbit of Earth for communication 1 19 10 Ion Stoica CS162 UCB Spring 2010 Every piece of computer hardware different Different CPU Pentium PowerPC ColdFire ARM MIPS Different amounts of memory disk Different types of devices Mice Keyboards Sensors Cameras Fingerprint readers touch screen Different networking environment Cable DSL Wireless Firewalls Questions Does the programmer need to write a single program that performs many independent activities Does every program have to be altered for every piece of hardware Does a faulty program crash everything Does every program have access to all hardware 1 19 10 Lec 1 13 OS Tool Virtual Machine Abstraction Application Operating System Hardware Ion Stoica CS162 UCB Spring 2010 Lec 1 14 Interfaces Provide Important Boundaries software Virtual Machine Interface instruction set Physical Machine Interface hardware Software Engineering Problem Turn hardware software quirks what programmers want need Optimize for convenience utilization security reliability etc Why do interfaces look the way that they do What s the hardware interface physical reality What s the application interface nicer abstraction Should responsibilities be pushed across boundaries For Any OS area e g file systems virtual memory networking scheduling 1 19 10 Ion Stoica CS162 UCB Spring 2010 History Functionality Stupidity Bugs Management CS152 Machine interface CS160 Human interface CS169 Software engineering management RISC architectures Graphical Pipeline Architectures 1 19 10 Lec 1 15 Page 4 Ion Stoica CS162 UCB Spring 2010 Lec 1 16
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