INTRO TO COMP ENG CHAPTER XII 1 CHAPTER XII SINGLE CYCLE DPU CHAPTER XII SINGLE CYCLE DATAPATH UNIT READ SINGLE CYCLE DATAPATH FREE DOC ON COURSE WEBPAGE R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XII 2 SINGLE CYCLE DPU SINGLE CYCLE DPU SINGLE CYCLE DPU INTRODUCTION INTRODUCTION From the previous chapter we now have a number of datapath elements such as Register file RF Adder subtractor unit AU Logical unit LU Shift unit SU The question now is how to take these datapath elements and form a datapath unit DPU The DPU that we will focus on in this chapter is a basic single cycle DPU using a triple bus internal architecture R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XII 3 SINGLE CYCLE DPU SINGLE CYCLE DPU SINGLE CYCLE DPU INTRODUCTION DATAPATH ELEMENTS For our examples we will use the following 32 bit type DPU elements Adder Subtractor Unit AU Register File RF 5 5 5 32 Zwa Xra Yra Clk A 32 32 32 X rwe 32x32 do RF Ydo 32 Zdi AU Logical Unit LU 32 B 32 A LU 32 B en a s en LF 32 32 F Shift Unit SU 32 A 4 SU en ST 32 F F These allow us to design a 32 bit word computer with 32 registers Of course other word sizes could be used for other designs R M Dansereau v 1 0 B 2 INTRO TO COMP ENG CHAPTER XII 4 SINGLE CYCLE DPU SINGLE CYCLE DPU ADD SUBTRACT MACHINE SINGLE CYCLE DPU INTRODUCTION DATAPATH ELEMENTS Below is a simple datapath with a register file and adder subtractor 5 5 5 Zwa Xra Yra Clk 32 X rwe 32x32 do 32 RF Ydo Zdi X bus Y bus A Datapath Z bus AU Important It only takes 1 clock cycle to add subtract and store the result B en a s 32 This structure is also known as a triple bus internal DPU architecture R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XII 5 SINGLE CYCLE DPU SINGLE CYCLE CPU ADD SUBTRACT MACHINE SINGLE CYCLE DPU INTRODUCTION DATAPATH ELEMENTS ADD SUBTRACT MACHINE This simple add subtract machine DPU allows us to add or subtract values in our registers and store the result back into another register For instance say that we wanted to add the contents of register R1 with register R2 and store the result back in register R3 R3 R1 R2 What control signals are required a s 0 and en 1 for AU Xra 00001 Yra 00010 Zwa 00011 and rwe 1 for RF These control signals are applied at the beginning of a clock cycle The signals then propagate forming the sum at the output of the AU At the end of the clock cycle the sum on Z bus is clocked into R3 R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XII 6 SINGLE CYCLE DPU SINGLE CYCLE CPU ADD SUBTRACT MACHINE SINGLE CYCLE DPU INTRODUCTION DATAPATH ELEMENTS ADD SUBTRACT MACHINE What if instead we wanted to perform the following operation R2 R1 R2 The control signals required are a s 0 and en 1 for AU Xra 00001 Yra 00010 Zwa 00010 and rwe 1 for RF What is the result of this if the current value of R1 0x00000001 and R2 0x00000003 The register R2 would be updated at the end of the clock cycle with the value 0x00000004 Remember the current value of R2 is put on the X or Y bus and it is only at the END of the clock cycle that the contents of R2 get changed R M Dansereau v 1 0 SINGLE CYCLE DPU INTRO TO COMP ENG CHAPTER XII 7 BASIC SINGLE CYCLE DPU SINGLE CYCLE DPU SINGLE CYCLE DPU INTRODUCTION DATAPATH ELEMENTS ADD SUBTRACT MACHINE A more useful single cycle datapath can be as follows 5 5 5 Zwa Xra Yra Clk rwe Zdi 32x32 Xdo RF Ydo 32 X bus Y bus 32 A AU B en a s Z bus A LU B en LF A 4 SU en ST 32 This structure is still a triple bus internal DPU architecture R M Dansereau v 1 0 B 2 INTRO TO COMP ENG CHAPTER XII 8 SINGLE CYCLE DPU SINGLE CYCLE CPU COMPUTATION EXAMPLES SINGLE CYCLE DPU DATAPATH ELEMENTS ADD SUBTRACT MACHINE BASIC SINGLE CYCLE DPU How does this change the additions we were doign earlier Say we want to again perform the following addition R3 R1 R2 The control signals we would need are a s 0 and en 1 for AU en 0 for LU en 0 for SU Xra 00001 Yra 00010 Zwa 00011 and rwe 1 for RF Notice that we use the same control signals as before but now include signals to disable the LU and SU during this addition clock cycle R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XII 9 SINGLE CYCLE DPU SINGLE CYCLE DPU COMPUTATION EXAMPLES SINGLE CYCLE DPU ADD SUBTRACT MACHINE BASIC SINGLE CYCLE DPU COMPUTATION EXAMPLES Another operation we might want to do with this DPU is perform a logical shift of the contents of R15 by a distance indicated in R6 The control signals required are en 0 for AU en 0 for LU en 1 and ST 00 for SU Xra 01111 Yra 00110 Zwa 01111 and rwe 1 for RF Notice that this set of control signals disables the AU and LU while enabling the SU The SU is set to do a logical shift with ST 00 The distance of the shift is according to what is in R6 The result is stored back in R15 with Zwa 01111 and rwe 1 for RF R M Dansereau v 1 0 SINGLE CYCLE DPU INTRO TO COMP ENG CHAPTER XII 10 ARITHMETIC LOGIC UNIT SINGLE CYCLE DPU SINGLE CYCLE DPU ADD SUBTRACT MACHINE BASIC SINGLE CYCLE DPU COMPUTATION EXAMPLES Since only one of AU SU or LU will be active at a time in this architecture we will combine to form an arithmetic logic unit ALU 32 32 A AU 32 B 32 A SU 32 B en a s en ST 32 32 32 2 F A LU B en LF 32 F R M Dansereau v 1 0 2 A asl 32 F 4 32 asl line 00 AU 01 SU 10 LU B ALU LF 4 ST 2 en a s 32 F SINGLE CYCLE DPU INTRO TO COMP ENG CHAPTER XII 11 SINGLE CYCLE DPU W ALU SINGLE CYCLE DPU SINGLE CYCLE DPU BASIC SINGLE CYCLE DPU COMPUTATION EXAMPLES ARITHMETIC LOGIC UNIT Using our ALU the DPU can be redrawn as follows 5 5 5 Zwa Xra Yra Clk rwe Zdi 32x32 Xdo RF Ydo 32 X bus Y bus 32 2 Z bus A asl B ALU LF 4 ST 2 en a s 32 This structure is still a triple bus internal DPU architecture R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XII 12 SINGLE CYCLE DPU SINGLE CYCLE DPU IMMEDIATE REGISTER SINGLE CYCLE DPU COMPUTATION EXAMPLES ARITHMETIC LOGIC UNIT SINGLE …
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