INTRO TO COMP ENG CHAPTER XI 1 CHAPTER XI DATAPATH ELEMENTS CHAPTER XI DATAPATH ELEMENTS READ DATAPATH ELEMENTS FREE DOC ON COURSE WEBPAGE R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XI 2 DATAPATH ELEMENTS DATAPATH ELEMENTS DATAPATH ELEMENTS INTRODUCTION INTRODUCTION So far we have discussed many small components and building blocks One final step in our building blocks before we can start to piece together a microprocessor is various datapath elements We have already discussed portions of these datapath elements in terms of other components and building blocks We will now consider some of these components and building blocks in ways that will make the design of a microprocessor a little easier in the next chapter R M Dansereau v 1 0 REGISTER FILES INTRO TO COMP ENG CHAPTER XI 3 REGISTER LAYOUT DATAPATH ELEMENTS DATAPATH ELEMENTS INTRODUCTION A general m n register file with m registers that are each n bits wide is illustrated below Data In n n Register 0 w0 Data Out r0 Register 1 w1 r1 Register m 1 wm 1 rm 1 The r k and w j signals indicate which register to read write respectively R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XI 4 DATAPATH ELEMENTS REGISTER FILES DATAPATH ELEMENTS REGISTER FILES REGISTER LAYOUT WRITE DECODER For writing to a register we include a write address with decoder Write Address Write Enable Decoder Data n In w 0 n Register 0 Data Out r0 Register 1 0 1 r1 w1 m 1 Register m 1 wm 1 rm 1 A given Write Address with Write Enable 1 selects which register 0 through m 1 to store the input from Data In R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XI 5 DATAPATH ELEMENTS READ DECODER DATAPATH ELEMENTS REGISTER FILES REGISTER LAYOUT WRITE DECODER For reading from a register we include a read address with decoder Data n Data n Register 0 In Out w0 r0 0 Register 1 Read w1 1 Address r1 Decoder REGISTER FILES Read Enable m 1 Register m 1 rm 1 wm 1 A given Read Address with Read Enable 1 selects which register 0 through m 1 to read from and output to Data Out Could have multiple data outputs with multiple read address decoders R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XI 6 DATAPATH ELEMENTS REGISTER FILES REGISTER FILES REGISTER LAYOUT WRITE DECODER READ DECODER 32 BIT WORD 32 REGISTERS For the upcoming datapath designs in the next chapter we want to have a 32x32 register file with one write input and two read outputs Xra X read address 5 5 5 Yra Y read address Zwa Z write address Clk Xdo X data out Ydo Y data out Zdi Z data in rwe register write enable Zwa Xra Yra rwe 32 Zdi 32x32 Xdo register file Ydo 32 32 Note Two data outputs implemented with two read address decoders R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XI 7 DATAPATH ELEMENTS ADDER SUBTRACTOR GENERAL UNIT DIAGRAM REGISTER FILES WRITE DECODER READ DECODER 32X32 REGISTER FILE An n bit adder subtractor unit is often illustrated as follows n Enable unit 1 or disable unit 0 n A B adder subtrator unit a s enable F n This unit would have n full adders internally R M Dansereau v 1 0 Select either addition 0 or subtraction 1 INTRO TO COMP ENG CHAPTER XI 8 ADDER SUBTRACTOR OTHER UNIT SIGNALS DATAPATH ELEMENTS REGISTER FILES ADDER SUBTRACTOR GENERAL UNIT DIAGRAM Other signals often included with an adder subtractor are shown below n Carry in or Borrow in n A B Cin a s enable Cout F n Carry out or Borrow out R M Dansereau v 1 0 Flags Overflow Negative F 0 Zero F 0 INTRO TO COMP ENG CHAPTER XI 9 DATAPATH ELEMENTS LOGICAL UNIT INTRODUCTION REGISTER FILES ADDER SUBTRACTOR GENERAL UNIT DIAGRAM OTHER UNIT SIGNALS A useful unit would be one that can take two n bit inputs and perform some logical operation between each of the bits to get an n bit output For example given the 8 bit values 0001 1110 and 1001 1000 we might want to find the bit wise logical OR 0001 1110 bit wise 1001 1000 logical OR 1001 1110 Or similarly the bit wise logical AND of the two 8 bit values 0001 1110 bit wise logical AND 1001 1000 0001 1000 These types of operations are often used for masking and setting bits R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XI 10 DATAPATH ELEMENTS LOGICAL UNIT GENERAL UNIT DIAGRAM REGISTER FILES ADDER SUBTRACTOR LOGICAL UNIT INTRODUCTION Below is a general unit diagram for an n bit logical unit n Enable unit 1 or disable unit 0 n A B logical unit enable LF F Logical Function LF 4 on 2 bits n Logical operations such as AND OR NOT NAND NOR etc are done for each bit of A and B to form F R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XI 11 DATAPATH ELEMENTS LOGICAL UNIT 4 BIT LOGICAL FUNCTIONS LF ADDER SUBTRACTOR LOGICAL UNIT INTRODUCTION GENERAL UNIT DIAGRAM Recall the possible logic functions for two bits A and B We can use the column Fn as the 4 bit LF input for the logical unit A B F 0 F 1 F 2 F 3 F 4 F 5 F 6 F 7 F 8 F 9 F 10 F 11 F 12 F 13 F 14 F 15 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 AB Null A A B A B Inhibition R M Dansereau v 1 0 B A B A B B A Implication AB 1 Identity INTRO TO COMP ENG CHAPTER XI 12 DATAPATH ELEMENTS LOGICAL UNIT BIT SLICE IMPLEMENTATION LOGICAL UNIT INTRODUCTION GENERAL UNIT DIAGRAM 4 BIT LOGICAL FUNCTIONS A number of internal implementations exist for the logical unit The easiest is to use a 4 to 1 multiplexer for each bit as follows Module Enable Require n of these to form our n bit logical unit Take Fn column from previous slide as LF input LF0 0 LF1 1 LF2 LF3 2 3 4X1 MULTIPLEXER E S1 S0 A B R M Dansereau v 1 0 F Note When you look at a design for each bit it is known as a bit slice INTRO TO COMP ENG CHAPTER XI 13 DATAPATH ELEMENTS BIT SLICE IMPLEMENTATION LOGICAL UNIT GENERAL UNIT DIAGRAM 4 BIT LOGICAL FUNCTIONS BIT SLICE IMPLEMENTAT The following are example LF inputs for a logical unit bit slice Module Enable E 0 0 1 1 A B R M Dansereau v 1 0 NAND function 1 …
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