INTRO TO COMP ENG CHAPTER VII 1 CHAPTER VII SEQUENTIAL SYSTEMS CHAPTER VII SEQUENTIAL SYSTEMS LATCHES REGISTERS R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 2 SEQUENTIAL SYST SEQUENTIAL SYSTEMS SEQUENTIAL SYSTEMS INTRODUCTION INTRODUCTION So far So far we have dealt only with combinational logic where the output is formed from the Input Combinational Output Logic current input Sequential systems Sequential systems extend the idea of combinational logic by including a system state or in other words memory to our system This allows our system to perform operations that build on past operations in a sequential manner i e one after another Timing diagrams will be needed to analyze the operation of many sequential systems R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 3 SEQUENTIAL SYSTEMS SEQUENTIAL SYST SEQUENTIAL SYSTEMS INTRODUCTION MEALY MOORE MACHINES Mealy machine Sequential system where output depends on current Input input and state Sequential System Combinational Logic Output Memory state Moore machine Sequential system where output depends only on current state Input Sequential System Combinational Logic Memory state R M Dansereau v 1 0 Output INTRO TO COMP ENG CHAPTER VII 4 STORING BITS STORING A BIT SEQUENTIAL SYSTEMS SEQUENTIAL SYSTEMS INTRODUCTION MEALY MOORE Since there are propagation delays in real components this time delay can be used to store information For instance the following buffer has a propagation delay of t pd A F tpd Timing Diagram A F tpd R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 5 SEQUENTIAL SYSTEMS STORING BITS FEEDBACK LOOPS SEQUENTIAL SYSTEMS STORING BITS STORING A BIT If we wish to store data for an indefinite period of time then a feedback loop can be used to maintain the bit 0 0 Can also use two inverters tpd 1 1 tpd How do we get the bit in there R M Dansereau v 1 0 1 tpd 2 1 tpd 2 INTRO TO COMP ENG CHAPTER VII 6 SEQUENTIAL SYSTEMS STORING BITS LOADING A BIT SEQUENTIAL SYSTEMS STORING BITS STORING A BIT FEEDBACK LOOPS To store a bit we need a way of loading an input bit into the structure and making breaking the connection in the feedback look One way of breaking connections is to use transmission gates S1 A TG S2 Note The latch is level sensitive TG If A changes while S1 1 then Q will change as well Q Q A gets temporarily stored in the inverters when S 1 1 and S 2 0 Then setting S 1 0 and S 2 1 A gets held in the feedback loop R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 7 SEQUENTIAL SYSTEMS LATCHES D LATCH WITH TG STORING BITS STORING A BIT FEEDBACK LOOPS LOADING A BIT The previous example is a data latch D latch if both S 1 and S 2 are controlled by a single line C as follows Note The latch is level sensitive C Enable TG D TG If D changes while C 1 then Q will change as well Q Q The control line C might be derived from the clock signal or a signal from the controller sequencer in the microprocessor R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 8 LATCHES SEQUENTIAL SYSTEMS SR LATCH NAND GATES LATCHES D LATCH WITH TG NAND PRIMITIVES CONSTRUCTING A LATCH NAND gates can also be used to create a latch this time an SR latch S set R reset Q Q S 1 1 0 1 0 R 0 1 1 1 0 Q 0 0 1 1 1 Q 1 1 after S 1 R 0 0 0 after S 0 R 1 1 Recall A B NAND 0 0 1 0 1 1 1 0 1 1 1 0 Notice that this latch is level sensitive R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 9 SEQUENTIAL SYSTEMS LATCHES SR LATCH NOR GATES LATCHES CONSTRUCTING A LATCH S R LATCH NAND GATES MIXED LOGIC EQUIV The SR latch also uses feedback to store a bit R reset S set Q Q S 1 0 0 0 1 R 0 0 1 0 1 Q 1 1 0 0 0 Q 0 0 after S 1 R 0 1 1 after S 0 R 1 0 Recall A B NOR 0 0 1 0 1 0 1 0 0 1 1 0 Notice that this latch is level sensitive R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 10 SEQUENTIAL SYSTEMS LATCHES SR LATCH WITH CONTROL LATCHES S R LATCH NAND GATES MIXED LOGIC EQUIV SR LATCH NOR GATES A control line can be added to the SR latch as follows forming an SR latch S S Q Enable R Q R This control line makes it possible to decide when the inputs S and R are allowed to change the state of the latch R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 11 LATCHES SEQUENTIAL SYSTEMS D LATCH WITH SR LATCH LATCHES MIXED LOGIC EQUIV SR LATCH NOR GATES SR LATCH W CONTROL A D latch can be implemented using what is effectively the SR latch with a control line as follows D S Q Enable R Q Note that as long as C 1 that the latch will change according to the value of D R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 12 SEQUENTIAL SYSTEMS LATCHES TIMING DIAGRAMS LATCHES SR LATCH NOR GATES SR LATCH W CONTROL D LATCH Timing diagrams allow you to see how a sequential system changes with time using different inputs For instance a timing diagram for a D latch might look like the following Enable D Q Q Time R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER VII 13 SEQUENTIAL SYSTEMS LATCHES TRANSPARENCY 1 LATCHES SR LATCH W CONTROL D LATCH TIMING DIAGRAMS Latches like the D latch are termed transparent or level sensitive This is because when enabled the output follows the input Enable IN Transparent Latch D OUT Q Enable R M Dansereau v 1 0 Q Note Transparent LATCHES INTRO TO COMP ENG CHAPTER VII 14 TRANSPARENCY 2 SEQUENTIAL SYSTEMS LATCHES D LATCH TIMING DIAGRAMS TRANSPARENCY The following behaviour is observed for Enable 0 and Enable 1 IN When Enable 0 input disconnected and stored bit outputed Transparent Latch OUT When Enable 1 latch acts like wire Enable Stored bit IN OUT 0 R M Dansereau v 1 0 IN OUT 1 INTRO TO COMP ENG CHAPTER VII 15 SEQUENTIAL SYSTEMS LATCH EXAMPLE PROBLEMS W TRANSPARENCY LATCHES D LATCH TIMING DIAGRAMS TRANSPARENCY A problem with latches is that they are level sensitive A momentary change of input changes the value passed out of the latch This is a problem if the input of a latch depends on the output of the same latch Example Design a system that flips a stored bit whenever Enable goes high An inexperienced engineer might design the following How will this design behave Transparent Latch Enable R M Dansereau v 1 0 Will the bit flip once when …
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