INTRO TO COMP ENG CHAPTER XIII 1 CHAPTER XIII ISA CHAPTER XIII INSTRUCTION SET ARCHITECTURE ISA READ INSTRUCTIONS FREE DOC ON COURSE WEBPAGE R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XIII 2 ISA ISA ISA INTRODUCTION INTRODUCTION We have now considered the beginnings of the internal architecture of a computer With this we considered microcode operations for performing simple data routing and calculations in one clock cycle As a programmer we don t want to interface with the microprocessor and manually send each and every control signal as is done with microcode We would prefer to abstract the instruction sent to the microprocessor Let the microprocessor designer handle the decoding of the abstracted instruction into the microcode control operations Start to define an assembly langauge MIPS R3000 4000 R M Dansereau v 1 0 PROGRAM PATH INTRO TO COMP ENG CHAPTER XIII 3 TRANSLATING CODE ISA ISA INTRODUCTION Below is the process for translating a program to machine opcodes High level program e g C C Pascal Java Compiler translates program add 10 8 9 xor 13 11 12 lw 15 0 16 Assembly language program Assembler converts to machine code 01011000101011101001001 10010101001101011101101 00101110100101010111011 R M Dansereau v 1 0 Machine instructions INTRO TO COMP ENG CHAPTER XIII 4 ISA PROGRAM PATH EXECUTING CODE ISA PROGRAM PATH TRANSLATING CODE Once the opcodes are given to the microprocessor it translates the opcode instructions to the microcodes operations we discussed Machine opcodes sent to microprocessor 01011000101011101001001 10010101001101011101101 00101110100101010111011 Machine Instructions Instruction Decoder Instruction decoder translates opcodes to the microcodes Microprocessor DPU R M Dansereau v 1 0 MIPS ASSEMBLY INTRO TO COMP ENG CHAPTER XIII 5 MIPS REGISTER NAMES ISA ISA PROGRAM PATH TRANSLATING CODE EXECUTING CODE For MIPS assembly many registers have alternate names or specific uses Register 0 1 2 3 4 7 8 15 16 23 24 25 26 27 28 29 30 31 R M Dansereau v 1 0 Name s zero v0 v1 a0 a3 t0 t7 s0 s7 t8 t9 gp sp fp ra Use always zero 0x00000000 reserved for assembler results and expression evaluation arguments temporary values saved values temporary values reserved for operating system global pointer stack pointer frame pointer return address INTRO TO COMP ENG CHAPTER XIII 6 ISA MIPS ASSEMBLY BASIC INST FORMAT ISA PROGRAM PATH MIPS ASSEMBLY MIPS REGISTER NAMES Need to consider an assembly language example We will use the MIPS R3000 4000 assembly so that you can refer to the Instruction free doc MIPS R3000 4000 assembly instruction format The majority of MIPS instructions have the following assembly language instruction format inst mnemonic destination source 1 source 2 You can see that this instruction format fits the register transfer level notation discussed with the single cycle DPU R18 R12 R15 destination R M Dansereau v 1 0 source 1 source 2 INTRO TO COMP ENG CHAPTER XIII 7 ISA MIPS ASSEMBLY REGISTER FORMAT INST PROGRAM PATH MIPS ASSEMBLY MIPS REGISTER NAMES BASIC INST FORMAT Register format R format instructions Many MIPS instructions have the following format for register to register type binary operations instr write register read register 1 read register 2 An example of this is add 10 8 9 This is the same as with our register transfer level operation R10 R8 R9 R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XIII 8 ISA MIPS ASSEMBLY REGISTER INSTRUCTIONS MIPS ASSEMBLY MIPS REGISTER NAMES BASIC INST FORMAT REGISTER INST FORMAT Below is the basic list of register format MIPS instructions Instruction Interpretation add 10 8 9 R10 R8 R9 sub 10 8 9 R10 R8 R9 and 10 8 9 R10 R8 and R9 or 10 8 9 R10 R8 or R9 xor 10 8 9 R10 R8 xor R9 sa 10 8 9 shift arithmetic Shift R8 by R9 and store in R10 sl 10 8 9 shift logical Shift R8 by R9 and store in R10 rot 10 8 9 rotate Rotate R8 by R9 and store in R10 lw 10 0 8 R10 M 0 R8 sw 10 0 8 M 0 R8 R10 R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XIII 9 ISA MIPS ASSEMBLY IMMEDIATE INST FORMAT MIPS ASSEMBLY BASIC INST FORMAT REGISTER INST FORMAT REGISTER INSTRUCTIONS Immediate format I format instructions Many MIPS instructions have the following format for register to register type binary operations instr write register read register immediate value Note No for last argument An example of this is addi 10 8 4 Again no for immediate value Note Include i to indicate an immediate value is used This is the same as with our register transfer level operation R10 R8 4 R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XIII 10 ISA MIPS ASSEMBLY IMMEDIATE INSTRUCTIONS MIPS ASSEMBLY REGISTER INST FORMAT REGISTER INSTRUCTIONS IMMEDIATE INST FORMAT Below is the basic list of immediate format MIPS instructions Instruction Interpretation addi 10 8 4 R10 R8 4 subi 10 8 4 R10 R8 4 andi 10 8 4 R10 R8 and 4 ori 10 8 4 R10 R8 or 4 xori 10 8 4 R10 R8 xor 4 sai 10 8 4 shift arithmetic Shift R8 by 4 and store in R10 sli 10 8 4 shift logical Shift R8 by 4 and store in R10 roti 10 8 4 rotate Rotate R8 by 4 and store in R10 lw 10 4 0 R10 M 4 R0 sw 10 4 0 M 4 R0 R10 R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XIII 11 ISA INST SET ARCH INSTRUCTION FORMATS MIPS ASSEMBLY REGISTER INSTRUCTIONS IMMEDIATE INST FORMAT IMMEDIATE INSTRUCTIONS How should the assembly be translated to machine code Instructions sent to microprocessor Machine Instructions Instruction Decoder Microprocessor DPU Have to consider what control signals the DPU requires How do we abstract from the DPU s requirements R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XIII 12 ISA INST SET ARCH OPCODES MIPS ASSEMBLY INSTRUCTION SET ARCH INSTRUCTION FORMATS First important part of a machine instruction is known as the operational codes opcodes An opcode indicates what major operation to perform Example major operations add subtract AND OR NOT XOR shift Once all major operations are identified for a processor design assign binary codes to each of the operation For example say that we want to design a machine that can perform 40 different types of major operations Then we would require at least 6 bits to represent all of the opcodes R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER XIII 13 ISA INST SET ARCH MIPS ASSEMBLY INSTRUCTION SET ARCH INSTRUCTION FORMATS OPCODES SAMPLE MIPS OPCODES Some example opcodes used in the MIPS processors are as follows Instruction Assigned Opcode Value add 10 8 9 100000 sub 10 8 9 100010 and 10 8 9 100100 or 10 8 9 100101 lw 10 0 8 100011 sw 10 0 8 101011 addi 10 8 4 001000 nop no