INTRO TO COMP ENG CHAPTER X 1 CHAPTER X MEMORY SYSTEMS CHAPTER X MEMORY SYSTEMS READ MEMORY NOTES ON COURSE WEBPAGE CONSIDER READING PAGES 285 310 FROM MANO AND KIME OTHER USEFUL RAM MATERIAL AT ARS TECHNICA R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 2 MEMORY SYSTEMS MEMORY SYSTEMS MEMORY SYSTEMS INTRODUCTION INTRODUCTION A number of different types of memories and programmable logic devices exist Random access memory RAM Read only memory ROM Memories Programmable logic devices PLDs Programmable logic arrays PLAs Programmable array logic PAL Two level combinational networks Programmable gate arrays PGAs Programmable sequential arrays PSAs Field programmable gate arrays FPGAs Due to time limitations we will only cover RAM R M Dansereau v 1 0 combinational and sequential Multi level networks Two level INTRO TO COMP ENG CHAPTER X 3 MEMORY SYSTEMS MEMORY SYSTEMS MEMORY SYSTEMS INTRODUCTION TYPES OF RAM Two main categories of random access memory RAM exist Static memory or static RAM SRAM Information bits are latched such as with a latch or a flip flop Typical SRAM implementations require 4 to 6 transistors Dynamic memory or dynamic RAM DRAM Information bits are stored in the form of electric charges on capacitors The capacitors will discharge over time Refreshing the memory cell is required before the capacitor has discharged to much of the electric charge Most DRAM implementations use 1 transistor and 1 capacitor R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 4 MEMORY SYSTEMS STATIC RAM SRAM CELLS 1 MEMORY SYSTEMS INTRODUCTION TYPES OF RAM An inefficient SRAM bit cell can be formed as follows Select word line TG D How many transistors required for this design 2 4 for inverters 2 2 for TGs 12 transistors Very expensive in terms of silicon real estate R M Dansereau v 1 0 TG D STATIC RAM INTRO TO COMP ENG CHAPTER X 5 SRAM CELLS 2 MEMORY SYSTEMS MEMORY SYSTEMS STATIC RAM SRAM CELLS The structure for a 6 transistor implementation of an SRAM 1 bit cell is as follows We will refer to this as the 6T design Select word line 6T design D D The select or word line chooses the bit cell when high When selected the new D D is latched into the feedback loop R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 6 MEMORY SYSTEMS STATIC RAM SRAM CELLS 3 MEMORY SYSTEMS STATIC RAM SRAM CELLS Of course the previous SRAM cell structure can be drawn as follows replacing each inverter with 2 transistors Select word line VDD 6T design D R M Dansereau v 1 0 D INTRO TO COMP ENG CHAPTER X 7 MEMORY SYSTEMS STATIC RAM SRAM CELLS 4 MEMORY SYSTEMS STATIC RAM SRAM CELLS A 4 transistor design for an SRAM bit cell is as follows Select word line VDD 4T design D D Notice replacement of pMOS transistors with load resistors This is for your own information We won t be testing on the 4T design R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 8 MEMORY SYSTEMS DYNAMIC RAM DRAM CELLS 1 MEMORY SYSTEMS STATIC RAM SRAM CELLS A dynamic RAM cell stores the bit as a charge in a capacitor This bit must be refreshed periodically 100s of times a second Select word line Transmission gate opens when selected to charge or discharge capacitor TG This charge stores the bit D How many transistors required for this design 2 1 for TG and 2 1 for inverter 4 transistors Still expensive considering the extra refresh circuitry required R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 9 MEMORY SYSTEMS DYNAMIC RAM DRAM CELLS 2 MEMORY SYSTEMS STATIC RAM DYNAMIC RAM DRAM CELLS The capacitor charging structure can be simplified as follows Select word line Transmission gate opens when selected to charge or discharge capacitor 1T design This charge stores the bit D This structure for a DRAM bit cell is what is used in practice in real implementations Very little chip real estate is used R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 10 MEMORY SYSTEMS MEMORY UNITS SPECIFICATION MEMORY SYSTEMS STATIC RAM DYNAMIC RAM DRAM CELLS Having developed bit cells either SRAM or DRAM bit cells they can now be pieced together forming a memory unit What do we want to specify in the design of a memory unit The number of bits This gives the total number of bits that the memory unit can store The grouping of bits into words Accessing 1 bit at a time might be inconvenient so grouping bits into words is often done Common examples of word bit sizes are 4 8 16 32 and 64 The number of words in the memory unit addressable words This is a function of the word size and total number of bits R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 11 MEMORY UNITS MEMORY SYSTEMS DESCRIPTION STATIC RAM DYNAMIC RAM MEMORY UNITS SPECIFICATION In describing the capacity of a memory unit the following is used addresses x word size Example 1Mx8 If a memory unit is described as 1Mx8 then it has 1M 2 20 1048576 addresses 8 bits per word at each address location 8 data lines for the 8 bit words 20 address lines to specify the 1M 2 20 1048576 addresses and 1048576 8 8388608 bits in the entire memory unit R M Dansereau v 1 0 INTRO TO COMP ENG CHAPTER X 12 MEMORY SYSTEMS MEMORY UNITS DYNAMIC RAM MEMORY UNITS SPECIFICATION DESCRIPTION DESCRIPTION EXAMPLES Some further examples of memory descriptions are given below Note that the last four columns are all described with the information in the first column Try to fill in the empy cells for the last two rows Memory Total bits 1Mx8 8388608 1048576 20 8 1Kx4 4096 1024 10 4 2Mx4 8388608 2097152 21 4 4Mx1 4194304 4194304 22 1 2Mx32 67108864 2097152 21 32 16Kx64 8Mx8 R M Dansereau v 1 0 of addresses address lines data lines MEMORY UNITS INTRO TO COMP ENG CHAPTER X 13 BLOCK DIAGRAM 1 MEMORY SYSTEMS MEMORY UNITS SPECIFICATION DESCRIPTION DESCRIPTION EXAMPLES Below is a general block diagram for a memory unit n data input lines k address lines Read Write k Memory unit R W 2k words n bits per word n data output lines The k address lines access a word in the memory for input or output To simplify drawing we now form buses of n or k lines R M Dansereau v 1 0 MEMORY UNITS INTRO TO COMP ENG CHAPTER X 14 BLOCK DIAGRAM 2 MEMORY SYSTEMS MEMORY UNITS DESCRIPTION DESCRIPTION EXAMPLES BLOCK DIAGRAM To conserve pins the following layout is more common in practice k address lines Read Write Enable k Memory unit 2k words R W CS n bits per word n data lines input and output The data lines are both input and output lines not simultaneously This is done by using tristate buffers to form a tristate bus or sometimes referred to as a three state bus R M Dansereau v 1 0 INTRO TO COMP