ECE2030 Introduction to Computer Engineering Lecture 11 Building Blocks for Combinational Logic 2 Decoders Encoders Comparators Prof Hsien Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech 1 to 2 Line Decoder D0 A A D1 D0 0 0 1 1 1 0 D1 D 0 A D1 A 2 N N to M Line Decoder 2 M D0 2 to 4 line D1 A1 decoder D2 A0 D3 A1 A0 D3 D2 D1 D0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 3 2 to 4 Line Decoder A1 A0 D0 D1 A1 A0 D3 D2 D1 D0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 D2 D 0 A1 A 0 D3 D1 A1A 0 D 2 A1 A 0 How about if no one should be enabled D3 A1A 0 4 2 to 4 Line Decoder w Enable D0 2 to 4 line D1 A1 decoder D2 A0 En E n A 1 A 0 D 3 D 2 D 1 D 0 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 D3 D 0 En A1 A 0 D1 En A1A 0 D 2 EnA1 A 0 D3 EnA1A 0 5 2 to 4 Line Decoder w Enable En E n A 1 A 0 D 3 D 2 D 1 D 0 A1 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 A0 D0 D1 D2 D 0 En A1 A 0 D3 D1 En A1A 0 D 2 EnA1 A 0 D3 EnA1A 0 6 3 to 8 Line Decoder Truth Table A 2 A 1 A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 7 3 to 8 Line Decoder Truth Table A 2 A 1 A 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 8 3 to 8 Line Decoder A0 A1 A2 D0 D0 A0 2 to 4 D 1 line A1 decoder D2 D3 En D1 D2 A2 A1 A0 D7 D6 D 5 D4 D3 D2 D 1 D 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 D6 1 1 0 0 1 0 0 0 0 0 0 D7 1 1 1 1 0 0 0 0 0 0 0 D3 D0 D4 A0 2 to 4 D 1 line A1 decoder D2 D3 En D5 9 Implementing Logic w Decoder F1 X Y Z m 1 2 6 7 F2 X Y Z M 0 1 2 3 5 7 D0 Z A0 3 to 8 Y A1 X A2 D1 F1 line D2 decoder D3 D4 D5 F2 D6 D7 10 BCD to 7 Segment Decoder Another kind of decoder A B C D BCD to 7Segment Decoder a a b b c c d d e e f f g g 11 BCD to 7 Segment Decoder Another kind of decoder A B C D BCD to 7Segment Decoder a a b b c c d d e e f f g g a f b g e c d 12 BCD to 7 Segment Decoder Decode 2 and show 0 0 1 0 A B C D BCD to 7Segment Decoder a 1 b 1 b c 0 c d 1 d e 1 e f 0 f g 1 g a a f b g e c d 13 BCD to 7 Segment Decoder Decode 4 and show 0 1 0 0 A B C D BCD to 7Segment Decoder a 0 b 1 b c 1 c d 0 d e 0 e f 1 f g 1 g a a f b g e c d 14 BCD to 7 Seg Decoder Truth Table A B C D a b c d e f g 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 2 0 0 1 0 1 1 0 1 1 0 1 3 0 0 1 1 1 1 1 1 0 0 1 4 0 1 0 0 0 1 1 0 0 1 1 5 0 1 0 1 1 0 1 1 0 1 1 6 0 1 1 0 0 0 1 1 1 1 1 7 0 1 1 1 1 1 1 0 0 0 0 8 1 0 0 0 1 1 1 1 1 1 1 9 1 0 0 1 1 1 1 0 0 1 1 All other inputs 0 0 0 0 0 0 0 1 0 15 Design Each Output Individually a 0 A B C D a 0 0 0 0 1 1 0 0 0 1 0 2 0 0 1 0 1 3 0 0 1 1 4 0 1 0 5 0 1 6 0 7 AB CD 00 01 11 10 00 1 0 1 1 1 01 0 1 1 0 0 0 11 0 0 0 0 0 1 1 10 1 1 0 0 1 1 0 0 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 All other inputs 0 1 0 a A BD ACD ABD A BC 16 Design Each Output Individually …
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