ECE2030b HW 5 v 2 Due Monday 10 21 during class ANSWERS Problem 1 Using Finite State Machine techniques design a circuit to Detect when sequential input X delivers 3 logic 1 s in a row Do not detect overlapping sequences Example Input 01101111011111001111110 Output 00000010000100000010010 A Draw a State Diagram showing all possible states and transitions B Draw a logic table for the Next State bits Ni and the Output bit Q as a function of Present State bits Pi and Input bit X C Draw Karnaugh maps for the separate outputs Ni and Q D Draw a logic diagram showing the necessary registers and combinatorial logic blocks A State Diagram Meely 0 0 No new 1 s seen State 00 1 0 One new 1 seen State 01 0 0 1 0 Two new 1 s seen State 10 Unused State 11 0 0 1 1 X 0 State Diagram Moore 1 One new 1 seen State 01 0 Output 0 0 No new 1 s seen State 00 Output 0 0 0 1 1 Two new 1 s seen State 10 Output 0 1 Three new 1 s seen State 11 Output 1 Check List 0 1 Does every state have exits defined for all inputs B Logic or Truth Tables Meely Present P1 0 0 0 0 1 1 1 1 State P0 0 0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 0 1 Next N1 0 0 0 1 0 0 0 0 State N0 0 1 0 0 0 0 0 0 Output Q 0 0 0 0 0 1 0 0 For Meely Machine output occurs while machine is in state 10 and X 1 Moore Machine Moore Present P1 0 0 0 0 1 1 1 1 State P0 0 0 1 1 0 0 1 1 Input X 0 1 0 1 0 1 0 1 Next N1 0 0 0 1 0 1 0 0 State N0 0 1 0 0 0 1 0 1 Output Q 0 0 0 0 0 0 1 1 For Moore Machine output occurs while machine is in state 11 for Q can be designed as a function of N1 N0 B Karnaugh Maps for Moore Machine N1 X P1 P0 0 1 00 0 0 01 0 1 11 0 0 N1 X P1 P0 P1 P0 X P1 XOR P0 10 0 1 Logic N0 X P1 P0 0 1 00 0 1 01 0 0 0 0 0 1 0 1 11 0 1 10 0 1 N0 X P0 P1 Q P1 P0 0 1 Q P0 P1 state P1 P0 note for Moore Machine Q is function of present D Logic Diagram Moore N1 P1 Q P1 Clock N0 P0 P0 Clock N0 X N1 Solution as a Meely Machine is also acceptable
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