ECE2030 Introduction to Computer Engineering Lecture 14 Sequential Logic Circuits Prof Hsien Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech Sequential Logic Circuits inputs Next State outputs Combinational circuits Storage Element Present State delay Sequential circuits Controller by a periodic clock or an event trigger Combinational logic circuits State information stored in memory Output is a function of inputs and present state Can be synchronous or asynchronous 2 State machine example A TV channel control 0 1 CH 2 CH 3 1 1 0 CH 1 0 3 Sequential Logic Circuits inputs Next State outputs Combinational circuits Storage Element Present State clock Synchronous Circuits use clock pulse to synchronize For a typical synchronous design data are latched into the storage upon clock transition edgetriggered 4 Closed Loop Logic for Storing Information 0 1 X X Tpd Tpd A buffer 5 SR Latch QN S Q R 6 SR Latch R Q QN S S R Q QN 0 0 Q Q No Change 0 1 0 1 Reset 1 0 1 0 Set 1 1 0 0 Undefined 7 SR Latch S Q QN R S R Q QN 0 0 1 1 Undefined 0 1 1 0 Reset 1 0 0 1 Set 1 1 Q Q No Change 8 SR Latch w Control S Q C QN R C S R Q QN 0 X X Q Q No Change 1 0 0 Q Q No Change 1 0 1 0 1 Reset 1 1 0 1 0 Set 1 1 1 1 1 Undefined 9 Issue of an SR Latch or SR Latch R Q QN S S R Q QN 0 0 Q Q 0 1 0 1 1 0 1 0 1 1 0 0 S R Q QN Race and Unstable 10 D Latch D Q C QN C D Q QN 0 X Q Q 1 0 0 1 1 1 1 0 11 D Latch Keeping Data for Read Q Q 12 D Latch Writing Data D D Q Q 13 10T D Latch w Transmission Gates En En Q D En Q 14 10T D Latch w Transmission Gates En 1 En D D En Q Q D Writing Data 15 10T D Latch w Transmission Gates En 0 En D D new En Q D Q D Writing Data 16 D Latch Symbol D En Q Q En D Q Q 0 X NC NC 1 0 0 1 1 1 1 0 NC No Change 17 Latch is Transparent D Latch is called transparent or level sensitive Output follows input instantaneously En D Q Q Transparent 18 Transparency Property D Q Transparent Latch En Latch acts like a Wire D Q D Q Storage Cell Storage Cell En En 0 1 19 Problem of Transparency D Q Transparent Latch Other Logic Circuits En A momentary input change tunnels through the latch and the entire circuitry What problem this can cause 20 Problem of Transparency D Q D Transparent Latch En 1 En D Q Oscillating Unstable Unstable 21 Eliminating Transparency D Q Transparent Latch En D Q Transparent Latch En Separating the input and output so they are independently controlled Only open one gate at a time to avoid tunneling 22 Behavior of Master Slave Latches D Q D Storage Cell En 0 En 1 D Q Storage Cell 1 1 En 0 Storage Cell 0 0 Q D Storage Cell En 1 Q 23 Behavior of Master Slave Latches D1 Q1 En D2 Q2 D1 En En D1 initialized to1 Q1 D2 Q2 A Toggle Cell will discuss more later 24 Behavior of Master Slave Latches D1 Q1 En D2 Q2 En En D1 input Q1 D2 Q2 25 Behavior of Master Slave Latches D1 Q1 En D2 Q2 En En D1 input Q1 D2 Q2 26 Flip Flop F F Input D1 Q1 D2 Q2 Output Enable or clock Input 1 bit Flip Flop Output Enable or clock 27 Negative Edge Triggered Flip Flop Input D1 Q1 D2 Q2 Output Enable or clock clock Input Q1 D2 Output 28 Positive Edge Triggered Flip Flop Input D1 Q1 D2 Q2 Output Enable or clock clock Input Q1 D2 Output 29 Positive Edge Triggered Flip Flop Input D1 Q1 D2 Q2 Output Enable or clock clock Input Q1 D2 Output 30 Flip Flops Symbols D Q C Q Positive Edge Triggered D Flip Flop D Q C Q Negative Edge Triggered D Flip Flop 31 Dual phase Non overlapped Clocks In reality enable control is not ideal Use dual phase clocks 1 and 2 to replace Enable and its inversion 1 2 Input Q1 D2 Output D2 follows 1 while Output follows 2 32 Dual Phase Non overlapped Clocks Input D1 Q1 D2 1 Input Q2 Output 2 1 bit Flip Flop 1 Output 2 33
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