HW 8 Due March 26 2004 ECE2030a Name GT Bring this homework to class on Friday March 26 HW 7 Finite State Machine Circuit Design 1 Design a synchronous circuit with a two bit counter output is C1 C0 negativeedge triggered that counts the number of 1 s in a row from input X When X 0 or a third 1 in a row is detected resets the counter output C1 C0 to 0 0 Example Input X and output Ci X C1 C0 0 0 1 01 1 10 1 00 1 01 0 00 0 00 1 01 X 0 00 1 01 1 10 1 01 1 10 Input Clock 1 00 C0 COUNTER Reset Input X Q Edge Triggered Latch 1 0 00 Enable Clock Q p 1 C1 0 00 HW 8 Due March 26 2004 ECE2030a Name GT 2 Complete the table below A 2M x 16 memory has 2M words of 16 bits Memory Total Bits of addresses 32M 32M 2M 4K 4M 1M 128K 1K 4M x 8 1M x 32 128K x 16 1K x 4 of address lines 22 20 17 10 of data lines 8 32 16 4 B 3 Show how to connect these 1M x 16 chips to make a 2M by 16 memory 20 A0 A19 Addr A20 Data CS R W R W 16 16 20 Addr Data CS R W The inverter is used as a 1 2 multiplexer one of 2 outputs is 1 based on a one bit binary code A0 Q0 Q1 p 2 16
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