ECE2030 Introduction to Computer Engineering Lecture 1 Overview Prof Hsien Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech ECE2030 Syllabus Instructor Prof Hsien Hsin Sean Lee Email leehs gatech edu Course web http www ece gatech edu leehs ECE2030 My office Klaus 2318 Teaching Materials Morris Mano and Charles Kime Logic and Computer Design Fundamentals the 4th edition Course notes and handouts check out course web TA to be announced later Attending classes is important 2 ECE2030 Syllabus Grading policy 3 Homework assignment 5 each 1 Programming assignment 10 3 in class exams 15 each 1 final exam 30 100 90 A 90 80 B 80 70 C 70 55 D 55 0 F Will scale All homework turn in in the first 5 minutes in class of the due day All exams closed books closed notes no calculator Honor code Use T Square http tsquare gatech edu for your homework and exam grades 3 Objective Digital Design Principle Number systems Boolean algebra Switch and CMOS design Combinational logic Logic gates Building blocks de mux de encoder shifters adder subtractor multiplier Logic minimization Mixed logic Sequential logic Latches Flip flops Counters State machines Mealy Moore machines 4 Objective Digital Design Principle Memory and Programmable Devices Register RAM ROM PLA PAL Architectural concept Instruction set architecture ISA Stored Program Computer and Sequential Control von Neumann architecture Datapath Branches Processor and Software Convention MIPS ISA Procedural calls Stack 5 Hierarchy of Computation Problem Problem Algorith Algorith ms ms Programming Programming in in High Level High Level Language Language Compiler Assembler Compiler Assembler Linker Linker Instruction Instruction Set Set Architecture Architecture ISA ISA Micro architecture Binary Binary Target Target Machine one one implementation implementation System architecture architecture Functional units units Building Building blocks blocks Gates Level Design Design Transistors Transistors Manufacturing Manufacturing 6 Hierarchy of Computation Problem Problem Algorith Algorith ms ms Programming Programming in in High Level High Level Language Language Compiler Assembler Compiler Assembler Linker Linker Instruction Instruction Set Set Architecture Architecture ISA ISA Micro architecture Binary Binary Target Target Machine one one implementation implementation System architecture architecture Functional units units Building Building blocks blocks Human Human Level Level System System Level Level RTL RTL Level Level Gates Level Design Design Logic Logic Level Level Circuit Circuit Level Level Silicon Silicon Level Level Transistors Transistors Manufacturing Manufacturing 7 Hierarchy of Computation Problem Problem Algorith Algorith ms ms Programming Programming in in High Level High Level Language Language Compiler Assembler Compiler Assembler Linker Linker Instruction Instruction Set Set Architecture Architecture ISA ISA Micro architecture Binary Binary Target Target Machine one one implementation implementation System architecture architecture Functional units units Building Building blocks blocks Human Human Level Level System System Level Level Gates Level Design Design RTL RTL Level Level Our Focus in 2030 Logic Logic Level Level Circuit Circuit Level Level Silicon Silicon Level Level Transistors Transistors Manufacturing Manufacturing 8 Zoom in a System Component 9 Switch G D S John Bardeen William Shockley Walter Brattain Circa 1947 Bell Labs Nobel Prize in Physics 1956 10 Inventors of Integrated Circuits The Tyranny of Numbers Challenge Robert Noyce Jack Kilby Nobel Prize in Physics 2000 11 Fairchild Traitorous 8 Gordon E Moore circa 1965 12 Moore s Law 90 nm 596 mm2 1 7 billions Montecito 10 m 13 5mm2 2 25 0 42millio ns Exponential growth Transistor count will be doubled every 18 months Gordon Moore Intel co founder 13 A Generic Intel based PC System Your CPU here 14 Dual Core Itanium 2 Montecito 15 Integrated Circuit Complexity Source Intel 16 Minimum Feature Size We are currently at 0 065 m 65nm and moving towards 0 045 m 17 Average Transistor Price per year Source Dataquest 18 Processor Market Segmentation High High Performance Performance e g e g Intel 32 64 AMD Itanium IBM POWER BlueGene Sun T1 etc Embedded Embedded low power low power e g e g ARM ARM MIPS MIPS Xscale Xscale Special Special purpose purpose e g e g DSP DSP NVidia 19 Analog Signal vs Digital So why Digital 20 Binary Signals So why Binary 21 Voltage Range of Binary Signals 5 0 Volts HIGH 1 HIGH 1 4 0 Volts 3 0 Volts 2 0 Volts 1 0 Volts LOW 0 LOW 0 0 0 Volts INPUT OUTPUT 22
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