ECE2030 Introduction to Computer Engineering Lecture 9 Combinational Logic Mixed Logic Prof Hsien Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech Logic Design Logic circuits Combinational Sequential N inputs inputs Combinational circuits M outputs outputs Combinational circuits Storage Element delay 2 Combinational Logic N inputs Combinational circuits M outputs Outputs at any time are determined by the input combination When input changed output changed immediately Note that real circuits are imperfect and have propagation delay A combinational circuit Performs logic operations that can be specified by a set of Boolean expressions Can be built hierarchically 3 Design Hierarchy Example X0 X1 X2 X3 X4 X5 X6 X7 X8 9 input Odd Function 9 input Odd Function Z Function Specification To detect odd number of 1 inputs i e Z 1 when there is an odd number of 1 present in the inputs X0 X1 X2 A0 3 input A1 B0 A2 Odd X3 X4 X5 A0 3 input A1 B0 A2 Odd X6 X7 X8 A0 3 input A1 B0 A2 Odd Function Function A0 3 input A1 A2 Odd Z Function Function How to design a 3 input Odd Function 4 Derive Truth Table for Desired Functionality A B C F 0 0 0 0 0 0 1 1 A BC 00 01 11 10 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 0 1 F A BC ABC A BC ABC 1 0 1 0 A BC BC A BC BC 1 1 0 0 1 1 1 1 A B C A B C A B C A B C 5 Design Hierarchy Example X0 X1 X2 X3 X4 X5 X6 X7 X8 9 input Odd Function 9 input Odd Function Z 3 input Odd function B0 A0 A1 A2 X0 X1 X2 A0 3 input A1 B0 A2 Odd X3 X4 X5 A0 3 input A1 B0 A2 Odd X6 X7 X8 A0 3 input A1 B0 A2 Odd Function Function A0 3 input A1 A2 Odd Z Function Function A0 B0 A1 A2 6 Combinational Logic Design Example F A B C D BC A D B C F A D 7 Mixed Logic Enable component reuse Allow a digital logic circuit designer to implement a combinational logic with Only NAND gates Only NOR gates Only NAND and NOR gates 8 DeMorgan s Law 9 Mixed Logic 1 Implement all ORs in the Boolean function Implement all ANDs in the Boolean function Forget all the inversion at this moment 10 Example Mixed Logic 1 F A B C D BC A D B C A D 11 Mixed Logic 2 Draw Vertical Bars in the circuits where all complements in the Boolean equation occur Draw a bubble on each Vertical Bar 12 Example Mixed Logic 2 F A B C D BC A D B C A D 13 Mixed Logic 3 Convert each gate to the desired gate If only NAND gate is available insert a bubble in front of the AND gate If only OR gate is available insert a bubble in front of the OR gate Using DeMorgan s Law in the process OR NAND by adding 2 bubbles on the inputs side of OR AND NOR by adding 2 bubbles on the inputs side of the AND 14 Example Mixed Logic 3 F A B C D BC A D Assume this design uses NAND gates only B C A D 15 Mixed Logic 4 Balance the bubbles on each wire i e even out the number of bubbles on every wire If there is odd number of bubbles on a wire add an inverter i e a bubble And remove those vertical bars with bubbles which are used to help only not in the circuits 16 Example Mixed Logic 4 F A B C D BC A D Assume this design uses NAND gates only B C A D 17 How about Inverters Inverters can be implemented by either a NAND or a NOR gate Wiring the inputs together 18 Example Mixed Logic Final F A B C D BC A D Assume this design uses NAND gates only B C A D 19 Example Mixed Logic Final F A B C D BC A D Assume this design uses NAND gates only B C A D 6 NAND gates are used 20 Mixed Logic How about build the prior circuits with only NOR gates 21 Example Mixed Logic 1 F A B C D BC A D B C A D 22 Example Mixed Logic 2 F A B C D BC A D B C A D Add vertical bar for each inversion 23 Example Mixed Logic 3 F A B C D BC A D Assume this design uses NOR gates only B C A D Convert each gate to a NOR 24 Example Mixed Logic 4 F A B C D BC A D Assume this design uses NOR gates only B C A D Balance number of Bubbles on each wire 25 Example Mixed Logic 4 F A B C D BC A D Assume this design uses NOR gates only B C A D Balance number of bubbles on each wire and substitute all gates to NOR 26 Example Mixed Logic Final F A B C D BC A D Assume this design uses NOR gates only B C A D 7 NOR gates are used 27 Mixed Logic Example II 1 F A B C A B C D C D B A Implement the logic circuits by ignoring all inversion 28 Mixed Logic Example II 2 F A B C A B C D C D B A Add vertical bar bubble for each inversion 29 Mixed Logic Example II 3 F A B C A B C D C D B A Assume this design uses NAND gates only 30 Mixed Logic Example II 4 F A B C A B C D C D B A Balance the bubbles for each wire w inverters 31 Mixed Logic Example II 5 F A B C A B C D C D B A Remove the vertical bars bubbles 32 Mixed Logic Example II 6 F A B C A B C D C D B A Replace all the gates to NAND gates 33 Mixed Logic Example II 7 F A B C A B C D C D B A Final mixed logic uses 11 NAND gates one of them is a triple input NAND gate 34 Mixed Logic Example III 1 F A CA BD B D A C mplement the logic circuits by ignoring all inversions Implement 35 Mixed Logic Example III 2 F A CA BD B D A C Add vertical bar bubble for each inversion 36 Mixed Logic Example III 3 F A CA BD B D A C Assume this design uses NOR gates only 37 Mixed Logic Example III 4 F A CA BD B D A C Balance the bubbles for each wire w inverters 38 Mixed Logic Example III 5 F A CA BD B D …
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