Instruction Fetch and Branching Web Reading Branching Instruction Fetch with no branching to start Program Counter 32 bit register 32 32 4 32 address Instruction Memory data 32 Instruction Register 32 bit register 32 Conditional Branching Formats beq RZ RX branch target bne RZ RX branch target I Format Instruction opcode Z X 16 bit branch offset Remember the offset is a signed number using 2 s complement IF branch taken then Program Counter PC becomes PC PC 4 4 offset ELSE PC PC 4 PC relative addressing Conditional Branching Formats j jump address jump statement unconditional jumps to another portion of the program J format Instruction 32 bits opcode 26 bit Jump Address JA Address is word address but we have a byte addressed memory Multiple JA by 4 to convert to a byte addressed memory Only have a 28 bit byte address and we need 32 Concatenate the upper four bits of the PC to 4 JA Pseudodirect Addressing Pseudodirect addressing has a limitation Must exist within 228 256Mbyte Address space jr RX RX is the put into the 32 bit PC which can jump to any location IF THEN STATEMENT High Level IF THEN Statement Assembly IF THEN Statement R3 32 sub R0 R0 R0 R2 2 addi R3 R0 32 IF R1 R2 addi R2 R0 2 R4 R3 R2 bne R1 R2 ELSE add R4 R3 R2 ELSE R4 R3 R2 R4 8 R4 j END ELSE ELSE sub R4 R3 R2 END ELSE sai R4 R4 3 WHILE LOOP STATEMENT High Level WHILE LOOP Assembly IF THEN Statement R2 32 sub R0 R0 R0 R3 0 addi R2 R0 32 R4 0 sub R3 R3 R3 while R2 R3 sub R4 R4 R4 R4 R4 R3 LOOP beq R2 R3 END LOOP add R4 R4 R3 R3 R3 1 addi R3 R3 1 R5 R4 AND R3 j LOOP END LOOP and R5 R4 R3 Add beq and j instructions to our datapath Add two control lines to the datapath beq 1 if branching instruction is to be executed 0 otherwise jmp sel 1 if jump instruction is to be executed 0 otherwise Add one output Zero to the Arithmetic Unit AU Zero 1 if result of AU is zero 0 otherwise opcode Z X 16 bit branch offset ZY I Format Instruction 5 5 Z rwe 32 5 X Y addresses RF Z bus beq 0 1 X Z X out Y out au en a s AU Zero Adding beq and j instructions to our datapath Program Counter 32 bit register 32 Branch Offset 32 32 4 0 ls 2 1 0 1 28 address ls 2 Instruction Memory data jmp sel 26 32 Instruction Register 32 bit register 32 beq Zero jump address Native Instructions These instructions can be directly implemented in our GT datapath R format add R1 R2 R3 sub R1 R2 R3 and R1 R2 R3 or R1 R2 R3 xor R1 R2 R3 sa R1 R2 R3 sl R1 R2 R3 rot R1 R2 R3 I format addi R1 R2 100 subi R1 R2 100 andi R1 R2 100 ori R1 R2 100 xori R1 R2 100 sai R1 R2 100 sli R1 R2 100 roti R1 R2 100 J format j Jump Target lw R1 R2 sw R1 R2 beq R1 R2 branch target Pseudoinstructions These are extra instructions that are provided by the assembler register indirect addressing is native to our datapath index addressing lw R10 100 R2 R10 M R2 100 sw R10 100 R2 M R2 100 R10 Index Address lw R10 100 R2 sw R10 100 R2 addi R2 R2 100 lw R10 R2 subi R2 R2 100 addi R2 R2 100 sw R10 R2 subi R2 R2 100 Other pseudoinstructions for GT Datapath bne ROP1 ROP2 Branch target already defined li RDEST immediate value Move the immediate imm value into RDEST la RDEST address Load computed address into RDEST move RDEST ROP1 move register ROP1 into RDEST Programming convention for GT Datapath Assembly Language REGISTER NUMBER NEW REGISTER NAME USAGE 0 1 2 7 8 15 zero at TBD t0 t7 Always a constant zero 16 23 s0 s7 Saved temporary preserved across procedure calls 24 25 t8 t9 Temporary not preserved across procedure calls 26 27 28 31 k0 k1 TBD RESERVED for OS kernal RESERVED FOR ASSEMBLER Used for procedure calls temporary not preserved across procedure calls
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