CSE477 L23 Memory Peripherals.1 Irwin&Vijay, PSU, 2001CSE477VLSI Digital CircuitsFall 2001Lecture 23: Peripheral Memory Circuitswww.cse.psu.edu/~cg477[Adapted in part from Rabaey’s Digital Integrated Circuits, ©Prentice Hall, 1995]CSE477 L23 Memory Peripherals.2 Irwin&Vijay, PSU, 2001Review: 4x4 SRAM MemoryA0Row DecoderBLWL[0]A1A2Column Decodersense amplifierswrite circuitry!BLWL[1]WL[2]WL[3]bit line precharge2 bit wordsclocking and controlenablereadprechargeCSE477 L23 Memory Peripherals.3 Irwin&Vijay, PSU, 2001Peripheral Memory Circuitryq Row and column decodersq Sense amplifiersq Read/write circuitryq Timing and controlCSE477 L23 Memory Peripherals.4 Irwin&Vijay, PSU, 2001Row Decodersq Collection of 2Mcomplex logic gates organized in a regular, dense fashionq (N)AND decoderWL(0) = !A9!A8!A7!A6!A5!A4!A3!A2!A1!A0…WL(511) = !A9A8A7A6A5A4A3A2A1A0q NOR decoderWL(0) = !(A9+A8+A7+A6+A5+A4+A3+A2+A1+A0)…WL(511) = !(A9+!A8+!A7+!A6+!A5+!A4+!A3+!A2+!A1+!A0)CSE477 L23 Memory Peripherals.5 Irwin&Vijay, PSU, 2001Dynamic NOR Row DecoderVddA0!A0A1!A1WL3WL2WL1WL0prechargeCSE477 L23 Memory Peripherals.6 Irwin&Vijay, PSU, 2001Dynamic NAND Row Decoder!A0A0!A1A1WL0prechargeWL1WL2WL3CSE477 L23 Memory Peripherals.7 Irwin&Vijay, PSU, 2001Split Row DecoderAddress<6:0>*7*7*8 *8!(!A0!A1!A2). . .!(A0A1A2)!(!(!A0!A1!A2) + !(!A3!A4!A5) +!A6)WL0WL0WL127WL127*128*128CSE477 L23 Memory Peripherals.8 Irwin&Vijay, PSU, 2001Pass Transistor Based Column DecoderBL3BL2BL1BL0Data2 input NOR decoderA1A0S3S2S1S0q Advantage: speed since there is only one extra transistor in the signal pathq Disadvantage: large transistor count!BL3!BL2!BL1!BL0!DataCSE477 L23 Memory Peripherals.9 Irwin&Vijay, PSU, 2001Tree Based Column DecoderBL3BL2BL1BL0!A0A0!A1A1Dataq Advantage: number of transistors drastically reducedq Disadvantage: delay increases quadratically with the number of sections (so prohibitive for large decoders)l fix with buffers, progressive sizing, combination of tree and pass transistor approaches!BL3!BL2!BL1!BL0!DataCSE477 L23 Memory Peripherals.10 Irwin&Vijay, PSU, 2001Bit Line Prechargingequalization transistor - speeds up equalization of the two bit lines by allowing the capacitance and pull-up device of the nondischarged bit line to assist in precharging the discharged lineStatic Pull-up PrechargeBL !BLclockClocked Precharge!BLBLCSE477 L23 Memory Peripherals.11 Irwin&Vijay, PSU, 2001Sense Amplifierstp = ( C * ∆V ) / Iavlargesmallmake ∆ V as small as possibleSAinputoutputUse sense amplifiers (SA) to amplify the small swing on the bit lines to the full rail-to-rail swing needed at the outputCSE477 L23 Memory Peripherals.12 Irwin&Vijay, PSU, 2001Latch Based Sense Amplifiersensebit linesisolatesense amplifier outputs∆V = 0.1Vdd∆V = VddCSE477 L23 Memory Peripherals.13 Irwin&Vijay, PSU, 2001Alpha Differential Amplifier/Latchsensesense_out∆V = Vdd!sense_outS3S2S1S0column decodersenseamplifierN2N3N4N5P1 P2P3 P4N1mux_outsenseprecharge!mux_out0->1Pre -> Closed)0->1off->onCSE477 L23 Memory Peripherals.14 Irwin&Vijay, PSU, 2001Read/Write CircuitryD: data (write) busR: read busW: write signalCS: column select(column decoder)Local W (write):BL = D, !BL = !Denabled by W & CSLocal R (read):R = BL, !R = !BLenabled by !W & CS!BL BLSADW!RRPrechargeLocal R/WCSCSE477 L23 Memory Peripherals.15 Irwin&Vijay, PSU, 2001Approaches to Memory TimingSRAM TimingSelf-TimedDRAM TimingMultiplexed AddressingRASCASRAS-CAS timingAddressBusmsb’s lsb’sRowAddr.ColumnAddr.AddressBusAddressAddress transitioninitiates memoryoperationCSE477 L23 Memory Peripherals.16 Irwin&Vijay, PSU, 2001SRAM Address Transition DetectionDELAYtdA0DELAYtdDELAYtdATD...A1AN-1VDDATDCSE477 L23 Memory Peripherals.17 Irwin&Vijay, PSU, 2001DRAM TimingCSE477 L23 Memory Peripherals.18 Irwin&Vijay, PSU, 2001SecondLevelCache(SRAM)Review: A Typical Memory HierarchyControlDatapathSecondaryMemory(Disk)On-Chip ComponentsRegFileMainMemory(DRAM)DataCacheInstrCacheITLB DTLBeDRAMSpeed (ns): .1’s 1’s 10’s 100’s 1,000’sSize (bytes): 100’s K’s 10K’s M’s T’sCost: highest lowestq By taking advantage of the principle of locality:l Present the user with as much memory as is available in the cheapest technology.l Provide access at the speed offered by the fastest technology.CSE477 L23 Memory Peripherals.19 Irwin&Vijay, PSU, 2001q Address issued by the data path has to be mapped (in hardware) into a cache addressq Cache block (aka line) – unit of read/write information in cacheq Cache mapping strategiesl Direct mapped- A word can be in only one block in the cache, so only have to compare its tag against that block’s tagl Block set associative- A word can be in two (or four or eight …), so have to compare its tag against the tags of those two (or four or eight …) cache blocks l Fully associative- A word can be in any block in the cache, so have to compare its tag against the tags of all of the blocks in the cacheCacheswhich word in the cache blockwhich cache block in the settagCSE477 L23 Memory Peripherals.20 Irwin&Vijay, PSU, 2001Two-Way Block Set Associative CacheTag Data=Tag Data=Address issued by CPUHit Desired wordSet 1 Set 2CSE477 L23 Memory Peripherals.21 Irwin&Vijay, PSU, 2001Translation Lookaside Buffers (TLBs)q Small caches used to speed up address translation in processors with virtual memoryq All addresses have to be translated before cache accessq I$ can be virtually indexed/virtually taggedCSE477 L23 Memory Peripherals.22 Irwin&Vijay, PSU, 2001TLB StructureAddress issued by CPU (page size = index bits + byte select bits)Tag Data=Tag Data=Hit Desired wordVA Tag PAMost TLBs are small(<= 256 entries)and thus fully associativecontent addressable memories (CAMs)HitCSE477 L23 Memory Peripherals.23 Irwin&Vijay, PSU, 2001CAM DesignRead/Write CircuitryHitmatch<0>match<1>match<2>match<3>match/write dataWL<0>WL<1>WL<2>WL<3>precharge/matchmatchWLbit bitword line<0>of data arrayCSE477 L23 Memory Peripherals.24 Irwin&Vijay, PSU, 2001Reliability and Yieldq Semiconductor memories trade-off noise margin for density and performanceThus, they are highly sensitive to noise (cross talk, supply noise)q High density and large die size causes yield problems# of good chips/waferYield = 100# of chips/waferY = [(1 – e–AD)/(AD)]2q Increase yield using error