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PSU CSE 477 - Designing for Speed

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CSE477VLSI Digital CircuitsFall 2003 Lecture 11: Designing for SpeedReview: CMOS Inverter: DynamicReview: Designing Inverters for PerformanceSwitch Delay ModelInput Pattern Effects on DelayHigh to Low Transition (VTC Curve)Low to High Transition (Delay Curve)Transistor SizingTransistor Sizing a Complex CMOS GateTransistor Sizing a Complex CMOS GateFan-In Considerationstp as a Function of Fan-InFast Complex Gates: Design Technique 1Fast Complex Gates: Design Technique 1Fast Complex Gates: Design Technique 2Fast Complex Gates: Design Technique 2Sizing and Input Ordering EffectsFast Complex Gates: Design Technique 3Fast Complex Gates: Design Technique 4Fast Networks: Design Technique 5 - Logical EffortIntrinsic Delay Term, pLogical Effort Term, gExample of Logical EffortExample of Logical EffortDelay as a Function of Fan-OutPath Delay of Complex Logic Gate NetworkPath Delay Equation DerivationPath Delay of Complex Logic Gates, con’tFast Complex Gates: Design Technique 6TG Logic PerformanceDelay of a TG ChainTG Delay OptimizationNext Lecture and RemindersCSE477 L11 Fast Logic.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 11: Designing for SpeedMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L11 Fast Logic.2 Irwin&Vijay, PSU, 2003Cray was a legend in computers … said that he liked to hire inexperienced engineers right out of school, because they do not usually know what’s supposed to be impossible.The Soul of a New Machine, Kidder, pg. 77CSE477 L11 Fast Logic.3 Irwin&Vijay, PSU, 2003Review: CMOS Inverter: DynamicVDDtpHL= f(Rn, CL)tpHL= 0.69 ReqnCLtpHL= 0.69 (3/4 (CL VDD)/ IDSATn)= 0.52 CL/ (W/Lnk’nVDSATn)VoutCLRnVin= VDDCSE477 L11 Fast Logic.4 Irwin&Vijay, PSU, 2003Review: Designing Inverters for Performance Reduce CLz internal diffusion capacitance of the gate itselfz interconnect capacitancez fanout Increase W/L ratio of the transistorz the most powerful and effective performance optimization tool in the hands of the designerz watch out for self-loading! Increase VDDz only minimal improvement in performance at the cost of increased energy dissipation Slope engineering - keeping signal rise and fall times smaller than or equal to the gate propagation delays and of approximately equal valuesz good for performancez good for power consumptionCSE477 L11 Fast Logic.5 Irwin&Vijay, PSU, 2003Switch Delay ModelAReqACintCintBRpARpARnBRnCLNORCLARnARpBRpBRnNANDCSE477 L11 Fast Logic.6 Irwin&Vijay, PSU, 2003Input Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transitionz both inputs go low- delay is 0.69 Rp/2 CL since two p-resistors are on in parallelz one input goes low- delay is 0.69 RpCL High to low transitionz both inputs go high- delay is 0.69 2RnCL Adding transistors in series (without sizing) slows down the circuitCLARnARpBRpBRnCintCSE477 L11 Fast Logic.7 Irwin&Vijay, PSU, 2003High to Low Transition (VTC Curve)ABF= ! (A & B)ABM1M2CintVGS1= VBVGS2= VA –VDS10123012A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->12-input NAND with0.5µ/0.25µ NMOS0.75µ/0.25µ PMOS The threshold voltage of M2is higher than M1due to the body effect (γ) because of CintVTn2= VTn0+ γ(√(|2φF| + Vint) - √|2φF|)since VSBof M2is not zero due to the presence of CintVTn1= VTn0DDSSweakerPUNVinVoutCSE477 L11 Fast Logic.8 Irwin&Vijay, PSU, 2003Low to High Transition (Delay Curve)-0.500.511.522.530 100 200 300 400A=B=1→0A=1→0, B=1A=1, B=1→0time, psecVoltage, VInput DataPatternDelay(psec)A=B=0→169A=1, B=0→162A= 0→1, B=150A=B=1→035A=1, B=1→076A= 1→0, B=1572-input NAND with0.5µm/0.25µm NMOS0.75µm/0.25µm PMOSCL= 10 fFCSE477 L11 Fast Logic.9 Irwin&Vijay, PSU, 2003Transistor SizingCLARnARpBRpBRnCintBRpARpARnBRnCLCint12211221Assuming Rp= RnCSE477 L11 Fast Logic.10 Irwin&Vijay, PSU, 2003Transistor Sizing a Complex CMOS GateDABCOUT = !(D + A • (B + C))ADBCCSE477 L11 Fast Logic.11 Irwin&Vijay, PSU, 2003Transistor Sizing a Complex CMOS GateOUT = !(D + A • (B + C))DABCDABC12222244123 x 3 = 9 – 2 (in bottom pfet)= 7 split across top two pfets6126CSE477 L11 Fast Logic.12 Irwin&Vijay, PSU, 2003Fan-In ConsiderationsDCBAABCDCLC3C2C1Distributed RC model(Elmore delay)tpHL= 0.69 Reqn(C1+2C2+3C3+4CL)Propagation delay deteriorates rapidly as a function of fan-in –quadratically in the worst case.CSE477 L11 Fast Logic.13 Irwin&Vijay, PSU, 2003tpas a Function of Fan-In0250500750100012502 4 6 8 10 12 14 16tpHLtpLHtp(psec)fan-inquadratic function of fan-inlinear function of fan-intp Gates with a fan-in greater than 4 should be avoided.CSE477 L11 Fast Logic.14 Irwin&Vijay, PSU, 2003Fast Complex Gates: Design Technique 1 Transistor sizingz as long as fan-out capacitance dominates, the pull down chain is like a distributed RC line soz Should all fets be of the same size?CLC3C2C1InNM1M2M3MNIn3In2In1CSE477 L11 Fast Logic.15 Irwin&Vijay, PSU, 2003Fast Complex Gates: Design Technique 1 Transistor sizingz as long as fan-out capacitance dominates, the pull down chain is like a distributed RC line soz Should all fets be of the same size?No, use progressive sizingM1 > M2 > M3 > … > MNThe fet closest to the outputshould be the smallest.CLC3C2C1InNM1M2M3MNIn3In2In1Can reduce delay by more than 20%; decreasing gains as technology shrinksCSE477 L11 Fast Logic.16 Irwin&Vijay, PSU, 2003Fast Complex Gates: Design Technique 2 Input re-orderingz When not all inputs arrive at the same time, the latest arrivingsignal should be driving the top or bottom fet?critical path critical pathC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CL110→1charged10→11 chargedCSE477 L11 Fast Logic.17 Irwin&Vijay, PSU, 2003Fast Complex Gates: Design Technique 2 Input re-orderingz When not all inputs arrive at the same time, the latest arrivingsignal should be driving the top or bottom fet?critical path critical pathC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CL110→1chargeddischargeddischargedcharged10→1chargedcharged1delay determined by time to discharge CLdelay determined by time to discharge CL, C1and C2 The latest arriving signal should be driving the fet closest to the output.CSE477 L11 Fast Logic.18 Irwin&Vijay, PSU, 2003Sizing and Input Ordering EffectsDCBAABCDCLC3C2C1Progressive sizing in pull-down chain gives up to a 23% improvement.Input ordering saves 5%critical path A –


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