CSE477 L12 Designing for Low Power.1 Irwin&Vijay, PSU, 2001CSE477VLSI Digital CircuitsSpring 2001Lecture 12: Designing for Low PowerVijay Narayananwww.cse.psu.edu/~cg477[Adapted in part from Rabaey’s Digital Integrated Circuits, ©Prentice Hall, 1995]CSE477 L12 Designing for Low Power.2 Irwin&Vijay, PSU, 2001Review: Designing Fast CMOS Gatesq Transistor sizingq Progressive transistor sizingl fet closest to the output is smallest of series fetsq Transistor orderingl put latest arriving signal closest to the outputq Logic structure reorderingl replace large fan-in gates with smaller fan-in gate networkq Buffer (inverter) insertionl separate large fan-in from large CLwith buffersl uses buffers so no more than four t-gates in seriesCSE477 L12 Designing for Low Power.3 Irwin&Vijay, PSU, 2001Why worry about power? -- Chip Power Densities0102030405060W/cm**21.5 1 0.8 0.6 0.35 0.25 0.18 0.13 0.1 0.07Process (microns)Hot plateFrom From BorkarBorkar, 1999, 1999CSE477 L12 Designing for Low Power.4 Irwin&Vijay, PSU, 2001Why worry about power ? -- Battery Size/WeightExpected battery lifetime increase over the next 5 years: 30 to 40%From From RabaeyRabaey, 1995, 199565 70 75 80 85 90 95 0 10 20 30 40 50 Rechargable LithiumYearNickel-CadmiumNi-Metal HydrideNominal Capacity (W-hr/lb)Battery(40+ lbs)CSE477 L12 Designing for Low Power.5 Irwin&Vijay, PSU, 2001Technology Directions: SIA Roadmap2.42.22.02.42.01.4Battery power (W)18317417016013090High-perf power (W)0.60.60.91.21.51.8Power supply (V)109-1098-97-86-7Wiring levels2200180014001100800600Clock rate (MHz)14721408128010241024768Signal pins/chip354308269235170-214170Chip size (mm2)7012841154714-267Mtrans/cm2355070100130180Feature size (nm)201420112008200520021999YearFor Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years)http://www.itrs.net/ntrs/publntrs.nsfCSE477 L12 Designing for Low Power.6 Irwin&Vijay, PSU, 2001Why Power Mattersq Packaging costs; cooling costsq Power supply rail designq Digital noise immunityq Battery life (in portable systems)q Environmental concernsl Office equipment accounted for 5% of total US commercial energy usage in 1993l Energy Star compliant systemsCSE477 L12 Designing for Low Power.7 Irwin&Vijay, PSU, 2001Figures of Meritq Power consumption in Wattsl determines battery life in hoursl sets packaging limitsq Peak powerl determines power ground wiring designsl impacts signal noise margin and reliability analysisq Energy efficiency in Joulesl rate at which energy is consumed over timeq Energy = power * delayl joules = watts * secondsl lower energy number means less power to perform a computation at the same frequencyCSE477 L12 Designing for Low Power.8 Irwin&Vijay, PSU, 2001Power versus EnergyWattstimePower is height of curveWattstimeEnergy is area under curveApproach 1Approach 2Approach 2Approach 1Lower power design could simply be slowerCSE477 L12 Designing for Low Power.9 Irwin&Vijay, PSU, 2001PDP and EDPq Power-delay product (PDP) = Pav* tdl PDP is the average energy consumed (Wsec = Joule)l lower power design could simply be a slower designq Energy-delay product (EDP) = PDP * tdl EDP is the average energyconsumed multiplied by the computation time requiredl takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increase delay, but decrease energy consumption)l allows one to understand tradeoffs better0510150.5 1 1.5 2 2.5Vdd (V)Energy-Delay (normalized)CSE477 L12 Designing for Low Power.10 Irwin&Vijay, PSU, 2001Understanding TradeoffsEnergy1/Delayabcdq Which design is the “best” (fastest, coolest, both) ?CSE477 L12 Designing for Low Power.11 Irwin&Vijay, PSU, 2001Understanding TradeoffsEnergy1/DelayabcdLower EDPq Which design is the “best” (fastest, coolest, both) ?CSE477 L12 Designing for Low Power.12 Irwin&Vijay, PSU, 2001Where Does Power Go in CMOS?q Dynamic Power Consumptionl charging and discharging capacitorsq Short Circuit Currentsl short circuit path between supply rails during switchingq Leakage Currentl leaking diodes and transistorsq Static Currentsl design styles such as pseudo NMOSCSE477 L12 Designing for Low Power.13 Irwin&Vijay, PSU, 2001CMOS Gate Energy & Power EquationsE = CLVDD2 P0→1+ tscVDDIpeakP0→1 + VDDIleakageP = CLVDD2f0→1 + tscVDDIpeakf0→1 + VDDIleakageDynamic term(~90% today and decreasing relatively)Short-circuit term(~8% today and decreasing absolutely)Leakage term(~2% today and increasing)f0→1= P0→1* fclockCSE477 L12 Designing for Low Power.14 Irwin&Vijay, PSU, 2001Dynamic Power ConsumptionEnergy/transition = CL * VDD2 * P0→1Power = Energy/transition * f = CL* VDD2 * P0→1* fNot a function of transistor sizes!Data dependent - a function of switching activity!Vin VoutCLVddf0→1CSE477 L12 Designing for Low Power.15 Irwin&Vijay, PSU, 2001Lowering Dynamic Powerq Reducing VDDhas a quadratic effect!l Has a negative effect on performance especially as VDDapproaches 2VTq Lowering CLl Improves performance as welll Keep transistors minimum size (keeps intrinsic capacitance (gate and diffusion) small)l Transistors should be sized only when CLis dominated by extrinsic capacitance (fanout and wires)q Reducing the switching activity, f0→1= P0→1* fl A function of signal statistics and clock ratel Impacted by logic and architecture design decisionsCSE477 L12 Designing for Low Power.16 Irwin&Vijay, PSU, 2001Inverter Normalized Energy0123451 1.5 2 2.5 3 3.5 4 4.5 5Normalized EnergyScaling factor SCL= Cext+ S Cintα=0α=1α=2α=5α = Cext/Cintspeed of all implementations is kept constant by adjusting the supply voltage: larger values of S mean lower values of the supply voltageCSE477 L12 Designing for Low Power.17 Irwin&Vijay, PSU, 2001Dynamic Power Consumption is Data Dependent011001010100OutBAStatic 2-input NOR GateAssume signal probabilitiesPA=1 = 1/2PB=1 = 1/2Then transition probabilityP0→1 = Pout=0 x Pout=1= 3/4 x 1/4 = 3/16CSE477 L12 Designing for Low Power.18 Irwin&Vijay, PSU, 2001NOR Gate Transition ProbabilitiesCLABBAP0→1 is a strong function of signal statisticsP0→1 = P0 x P1= (1-(1-PA)(1-PB))(1-PA)(1-PB)PAPB01 0 1CSE477 L12 Designing for Low Power.19 Irwin&Vijay, PSU, 2001Transition Probabilities for Some Basic Gates(1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)XOR(1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))OR(1 - PAPB) x PAPBANDPAPB x (1 -