CSE477VLSI Digital CircuitsFall 2003 Lecture 28: Design for TestTest ProceduresTesting Fabricated DesignsTwo Important Test PropertiesGenerating and Validating Test VectorsFault ModelsFault ModelsProblem with Stuck-at ModelProblem with Stuck-at ModelPath SensitizationPath SensitizationTest Problem SizeTest Problem SizeReducing Number of Test VectorsTest ApproachesScan Based TestScan Path FF ImplementationPolarity Hold Shift FFScan RegisterScan Path TestingBoundary Scan (JTAG)Built in Self Test (BIST)Stimulus Generator (LRSR)Response AnalyzerResponse AnalyzerBILBOBILBOBILBOUse of BILBOAd-Hoc TestMemory Self TestCSE477 L28 DFT.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 28: Design for TestMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L28 DFT.2 Irwin&Vijay, PSU, 2003Test Procedures Diagnostic testz used in debugging and defect localizationz can afford to spend time testing Production test - “go/no go”z used in chip production (wafer and/or packaged)z since have to test each part, must be fast Parametric testz [v, i] versus [0,1]z check parameters such as noise margins, Vt, tpat corners (range of temperatures and supply voltage variations)z usually done with special wafer drop-insCSE477 L28 DFT.3 Irwin&Vijay, PSU, 2003Testing Fabricated Designs Goals of design-for-test (DFT)z make testing of manufactured parts swift and comprehensive DFT mantraz Provide controllability and observability Components of DFT strategyz Provide test patterns that guarantee reasonable coveragez Provide circuitry to enable testingCSE477 L28 DFT.4 Irwin&Vijay, PSU, 2003Two Important Test Properties Controllability - measures the ease of bringing a node to a given condition using only the input pins Observability - measures the ease of observing the value of a node at the output pins Need both!z combinational circuits are both - so relatively easy to determine test patternsz state in sequential circuits problematic - so turn into a combinational circuit (or use self-test)CSE477 L28 DFT.5 Irwin&Vijay, PSU, 2003Generating and Validating Test Vectors Automatic test-pattern generation (ATPG)z for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output z majority of available tools: combinational networks onlyz sequential ATPG available from academic research Fault simulationz determines test coverage of proposed test-vector setz simulates correct network in parallel with faulty networks Both require adequate models of faults in CMOS integrated circuitsCSE477 L28 DFT.6 Irwin&Vijay, PSU, 2003Fault ModelsStuck-at modelssa0 - stuck at zero (short-circuit to GND)sa1 - stuck at one (short-circuit to Vdd)ABγαβZCCSE477 L28 DFT.7 Irwin&Vijay, PSU, 2003Fault ModelsStuck-at modelssa0 - stuck at zero (short-circuit to GND)sa1 - stuck at one (short-circuit to Vdd)ABγαβα - A sa1Zβ - A sa0 or B sa0Cγ - C sa1 or Z sa0CSE477 L28 DFT.8 Irwin&Vijay, PSU, 2003Problem with Stuck-at ModelA B Z1 10 -1 0BβABAZCSE477 L28 DFT.9 Irwin&Vijay, PSU, 2003Problem with Stuck-at ModelA B Z1 1 00 - 11 0 Zi-1output node floats(retains old value)BβABAZsequential effect - needs two vectors to ensure detectionCSE477 L28 DFT.10 Irwin&Vijay, PSU, 2003Path Sensitization Determine the input pattern that makes a fault controllable (triggers the fault) and observable (makes its impact visible at the output nodes)AUYsa0BCZDXEControllable:Observable:CSE477 L28 DFT.11 Irwin&Vijay, PSU, 2003Path Sensitization Determine the input pattern that makes a fault controllable (triggers the fault) and observable (makes its impact visible at the output nodes)ABCDEUYsa011111Z1X0Controllable: Try to set U to 1 → A = 1 and B = 1Observable: Propagate U to Z → X = 1 and E = 0CSE477 L28 DFT.12 Irwin&Vijay, PSU, 2003Test Problem Sizecomblogic moduleN inputsK outputs2Ninput patternscomblogic moduleN inputsK outputs2N+Minput patternsM state regsCSE477 L28 DFT.13 Irwin&Vijay, PSU, 2003Test Problem Sizecomblogic moduleN inputsK outputs2Ninput patternscomblogic moduleN inputsK outputs2N+Minput patternsM state regsN=20 → 1 million patterns1 µsec/pattern → 1 second testN=20, M=10 → 1 billion patterns1 µsec/pattern → 16 minute testCSE477 L28 DFT.14 Irwin&Vijay, PSU, 2003Reducing Number of Test Vectors Two features can be exploited to reduce the number of test vectors Redundancy - a single fault in the circuit is usually covered by several input patterns; detection of the fault requires only one Reduced fault coverage - relax the requirement that all faults be detected (95% to 99% fault coverage is typical)CSE477 L28 DFT.15 Irwin&Vijay, PSU, 2003Test Approaches Scan based test Self test Ad-hoc testingProblem is getting harder z increasing complexity and heterogeneous combination of modules in system-on-a-chip.z advanced packaging and assembly techniques extend problem to the board levelCSE477 L28 DFT.16 Irwin&Vijay, PSU, 2003Scan Based TestComblogicAregAComblogicBregBInScanin ScanoutOutrunφtestφrunφtestφTwo operational modesnormal mode (N-bit wide clocked registers)test mode (registers chained as a single serial shiftregister)CSE477 L28 DFT.17 Irwin&Vijay, PSU, 2003Scan Path FF ImplementationQ (&scanout)DQMrunφscanintestφCSE477 L28 DFT.18 Irwin&Vijay, PSU, 2003Polarity Hold Shift FFrunφflipfloplatchsystem dataQ!QscanintestAφscanout!scanouttestBφIntroduced at IBM and set as company policy for all designsCSE477 L28 DFT.19 Irwin&Vijay, PSU, 2003Scan RegisterFFTest!TestTestIn0Out0ScaninFFTest!TestTestIn1Out1FFTest!TestTestIn2Out2FFTest!TestTestIn3Out3ScanoutTestClockN cyclesscan inN cyclesscan out1 cycleevaluateCSE477 L28 DFT.20 Irwin&Vijay, PSU, 2003Scan Path TestingREG[5]REG[4]REG[3]REG[2]REG[0]REG[1]COMPOUTSCANINCOMPINSCANOUTABPartial scan can be more effective for pipelined datapathsCSE477 L28 DFT.21 Irwin&Vijay, PSU, 2003Boundary Scan (JTAG)Printed-circuit boardLogicscan pathnormal interconnectPackaged ICBonding PadScan-inScan-outsi soBoard testing becoming as problematic as chip testingCSE477 L28 DFT.22 Irwin&Vijay, PSU, 2003Built in Self Test (BIST) The circuit decides if the results are correct! Need a way to supply test patterns (stimulus generator) and to compare the circuit’s