CSE477 L21 Memories.1 Irwin&Vijay, PSU, 2001CSE477VLSI Digital CircuitsFall 2001Lecture 21: Memorieswww.cse.psu.edu/~cg477[Adapted in part from Rabaey’s Digital Integrated Circuits, ©Prentice Hall, 1995]CSE477 L21 Memories.2 Irwin&Vijay, PSU, 2001Review: Major Components of a ComputerProcessorControlDatapathMemoryDevicesInputOutputCSE477 L21 Memories.3 Irwin&Vijay, PSU, 2001SecondLevelCache(SRAM)A Typical Memory HierarchyControlDatapathSecondaryMemory(Disk)On-Chip ComponentsRegFileMainMemory(DRAM)DataCacheInstrCacheITLB DTLBeDRAMSpeed (ns): .1’s 1’s 10’s 100’s 1,000’sSize (bytes): 100’s K’s 10K’s M’s T’sCost: highest lowestq By taking advantage of the principle of locality:l Present the user with as much memory as is available in the cheapest technology.l Provide access at the speed offered by the fastest technology.CSE477 L21 Memories.4 Irwin&Vijay, PSU, 2001Semiconductor MemoriesElectrically-programmed (PROM)FLASHShift RegisterCAMDRAME2PROMFIFO/LIFOSRAM (cache, register file)Mask-programmedEPROMNon-Random AccessRandom AccessROMNVRWMRWMCSE477 L21 Memories.5 Irwin&Vijay, PSU, 2001Growth in DRAM Chip Capacity642561,0004,00016,00064,000256,0001010010001000010000010000001980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000Year of introductionKbit capacityCSE477 L21 Memories.6 Irwin&Vijay, PSU, 20011D Memory ArchitectureWord 0Word 1Word 2Word n-1Word n-2StorageCellm bitsn wordsS0S1S2S3Sn-2Sn-1Input/Outputn words → n select signalsWord 0Word 1Word 2Word n-1Word n-2StorageCellm bitsS0S1S2S3Sn-2Sn-1Input/OutputA0A1Ak-1DecoderDecoder reduces # of inputsk = log2nCSE477 L21 Memories.7 Irwin&Vijay, PSU, 20012D Memory ArchitectureA0Row DecoderA1Aj-1Sense Amplifiersbit lineword linestorage (RAM) cellRow AddressColumn AddressAjAj+1Ak-1Read/Write CircuitsColumn Decoder2k-jm2jInput/Output (m bits)amplifies bit line swingselects appropriate word from memory rowCSE477 L21 Memories.8 Irwin&Vijay, PSU, 20013D Memory ArchitectureRow AddrColumn AddrBlock AddrInput/Output (m bits)Advantages:1. Shorter word and/or bit lines2. Block addr activates only 1 block saving powerCSE477 L21 Memories.9 Irwin&Vijay, PSU, 2001Read Only Memories (ROMs)CSE477 L21 Memories.10 Irwin&Vijay, PSU, 2001Precharged MOS NOR ROMVddprechargeWL(0)WL(1)WL(2)WL(3)GNDGNDBL(0) BL(1) BL(2) BL(3)CSE477 L21 Memories.11 Irwin&Vijay, PSU, 2001Precharged MOS NOR ROMVddprechargeWL(0)WL(1)WL(2)WL(3)GNDGNDBL(0) BL(1) BL(2) BL(3)0→ 10→ 11 1 1 10 1 1 0CSE477 L21 Memories.12 Irwin&Vijay, PSU, 2001MOS NOR ROM LayoutMetal1 on top of diffusionBasic cell10λ x 7 λWL(0)GND (diffusion)Metal1PolysiliconOnly 1 layer (contact mask) is used to program memory array, so programming of the ROM can be delayed to one of the last process steps.WL(1)WL(2)WL(3)GND (diffusion)BL(0) BL(1) BL(2) BL(3)CSE477 L21 Memories.13 Irwin&Vijay, PSU, 2001Transient Model for NOR ROMWLBLCbitprechargecwordmetal1polyrwordWord line parasiticsResistance/cell: 35ΩWire capacitance/cell: 0.65 fFGate capacitance/cell: 5.10 fFBit line parasiticsResistance/cell: 0.15ΩWire capacitance/cell: 0.83 fFDrain capacitance/cell: 2.60 fFCSE477 L21 Memories.14 Irwin&Vijay, PSU, 2001Propagation Delay of NOR ROMq Word line delayl Delay of a distributed rc-line containing M cellstword= 0.38(rwordx cword) M2= 20 nsec for M = 512q Bit line delayl Assuming min size pull-down and 3*min size pull-up with reduced swing bit lines (5V to 2.5V)Cbit= 1.7 pF and IavHL= 0.36 mA sotHL= tLH= 5.9 nsecCSE477 L21 Memories.15 Irwin&Vijay, PSU, 2001Read-Write Memories (RAMs)q Static – SRAMl data is stored as long as supply is appliedl large cells (6 fets/cell) – so fewer bits/chipl fast – so used where speed is important (e.g., caches)l differential outputs (output BL and !BL) l use sense amps for performancel compatible with CMOS technologyq Dynamic – DRAMl periodic refresh requiredl small cells (1 to 3 fets/cell) – so more bits/chipl slower – so used for main memoriesl single ended output (output BL only)l need sense amps for correct operationl not typically compatible with CMOS technologyCSE477 L21 Memories.16 Irwin&Vijay, PSU, 2001Memory Timing DefinitionsReadRead CycleRead Access Read AccessWriteWrite CycleDataWrite SetupData ValidWrite HoldCSE477 L21 Memories.17 Irwin&Vijay, PSU, 20014x4 SRAM MemoryA0Row Decoder!BLWL[0]A1A2Column Decodersense amplifierswrite circuitryBLWL[1]WL[2]WL[3]bit line precharge2 bit wordsclocking and controlenablereadprechargeBL[i] BL[I+1]CSE477 L21 Memories.18 Irwin&Vijay, PSU, 20012D Memory ConfigurationRow DecoderSense AmpsSense AmpsCSE477 L21 Memories.19 Irwin&Vijay, PSU, 2001Decreasing Word Line Delayq Drive the word line from both sidesq Use a metal bypassq Use silicidespolysilicon word linemetal word linedriverdriverWLpolysilicon word linemetal bypassWLCSE477 L21 Memories.20 Irwin&Vijay, PSU, 2001Decreasing Bit Line Delay (and Energy)q Reduce the bit line voltage swingl need sense amp for each column to sense/restore signalq Isolate memory cells from the bit lines after sensing (to prevent the cells from changing the bit line voltage further) - pulsed word linel generation of word line pulses very critical- too short - sense amp operation may fail- too long - power efficiency degraded (because bit line swing size depends on duration of the word line pulse)l use feedback signal from bit linesq Isolate sense amps from bit lines after sensing (to prevent bit lines from having large voltage swings) - bit line isolationCSE477 L21 Memories.21 Irwin&Vijay, PSU, 2001Pulsed Word Line Feedback Signalq Dummy columnl height set to 10% of a regular column and its cells are tied to a fixed valuel capacitance is only 10% of a regular columnRead Word lineBit linesCompleteDummybit lines10%populatedCSE477 L21 Memories.22 Irwin&Vijay, PSU, 2001Pulsed Word Line Timingq Dummy bit lines have reached full swing and trigger pulse shut off when regular bit lines reach 10% swing ReadCompleteWord lineBit lineDummy bit line∆V = Vdd∆V = 0.1VddCSE477 L21 Memories.23 Irwin&Vijay, PSU, 2001Bit Line IsolationsenseReadsense amplifierbit linesisolatesense amplifier outputs∆V = 0.1Vdd∆V = VddCSE477 L21 Memories.24 Irwin&Vijay, PSU, 20016-transistor SRAM Cell!BL