CSE477VLSI Digital CircuitsFall 2003 Lecture 02: Design MetricsCourse AdministrationGrading InformationSpecial AnnouncementOverview of Last LectureFundamental Design MetricsCost of Integrated CircuitsNRE Cost is IncreasingSilicon WaferRecurring CostsYield ExampleExamples of Cost Metrics (circa 1994)ReliabilityNoise in Digital Integrated CircuitsExample of Capacitive CouplingStatic Gate BehaviorDC Operation Voltage Transfer Characteristics (VTC)Mapping Logic Levels to the Voltage DomainNoise MarginsNoise MarginsThe Regenerative PropertyConditions for RegenerationNoise ImmunityDirectivityFan-In and Fan-OutThe Ideal InverterThe Ideal InverterDelay DefinitionsDelay DefinitionsModeling Propagation DelayPower and Energy DissipationPower and Energy DissipationSummaryDesign Abstraction LevelsDevice: The MOS TransistorCircuit: The CMOS InverterNext Lecture and RemindersCSE477 L02 Design Metrics.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 02: Design MetricsMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L02 Design Metrics.2 Irwin&Vijay, PSU, 2003Course Administration Instructor: Mary Jane [email protected]/~mji227 Pond LabOffice Hrs: T 16:00-17:00 & W 9:30-10:45 TA: Feihui Li Greg [email protected]@cse.psu.edu128 Hammond 226 Pond LabOffice Hrs: TBD TBD Labs: Accounts on 101 Pond Lab machines URL: www.cse.psu.edu/~cg477 Text: Digital Integrated Circuits, 2ndEdition Rabaey et. al., ©2003 Slides: pdf on the course web page after lectureCSE477 L02 Design Metrics.3 Irwin&Vijay, PSU, 2003Grading Information Grade determinatesz Midterm Exam ~25%- Monday, October 20th, 20:15 to 22:15, Location TBDz Final Exam ~25%- Monday, December 15th, 10:10 to noon, Location TBDz Homeworks/Lab Assignments (5) ~20%- Due at the beginning of class (or, if submitted electronically, by 17:00 on the due date). No late assignments will be accepted.z Design Project (teams of ~2) ~25%z In-class pop quizzes ~ 5% Please let me know about exam conflicts ASAP Grades will be posted on the course homepagez Must submit email request for change of grade after discussions with the TA (Homeworks/Lab Assignments) or instructor (Exams)z December 9thdeadline for filing grade corrections; no requests for grade changes will be accepted after this dateCSE477 L02 Design Metrics.4 Irwin&Vijay, PSU, 2003Special Announcement Hands on max tutorialz Tonight (September 9th)z 7:00 to 9:00pmz 101 Pond Labz Make sure you have your unix account informationCSE477 L02 Design Metrics.5 Irwin&Vijay, PSU, 2003Overview of Last Lecture Digital integrated circuits experience exponentialgrowth in complexity (Moore’s law) and performance Design in the deep submicron (DSM) era creates new challengesz Devices become somewhat differentz Global clocking becomes more challengingz Interconnect effects play a more significant rolez Power dissipation may be the limiting factor Our goal in this class will be to understand and design digital integrated circuits in advanced technologies (at or below 180 nanometer) Today we look at some basic design metricsCSE477 L02 Design Metrics.6 Irwin&Vijay, PSU, 2003Fundamental Design Metrics Functionality Costz NRE (fixed) costs - design effortz RE (variable) costs - cost of parts, assembly, test Reliability, robustnessz Noise marginsz Noise immunity Performancez Speed (delay)z Power consumption; energy Time-to-marketCSE477 L02 Design Metrics.7 Irwin&Vijay, PSU, 2003Cost of Integrated Circuits NRE (non-recurring engineering) costsz Fixed cost to produce the design- design effort- design verification effort- mask generationz Influenced by the design complexity and designer productivityz More pronounced for small volume products Recurring costs – proportional to product volumez silicon processing- also proportional to chip areaz assembly (packaging)z testfixed costcost per IC = variable cost per IC + -----------------volumeCSE477 L02 Design Metrics.8 Irwin&Vijay, PSU, 2003NRE Cost is IncreasingCSE477 L02 Design Metrics.9 Irwin&Vijay, PSU, 2003Silicon WaferSingle dieWaferFrom http://www.amd.comCSE477 L02 Design Metrics.10 Irwin&Vijay, PSU, 2003Recurring Costscost of die + cost of die test + cost of packagingvariable cost = ----------------------------------------------------------------final test yieldcost of wafercost of die = -----------------------------------dies per wafer × die yieldπ × (wafer diameter/2)2π × wafer diameterdies per wafer = ---------------------------------- − ---------------------------die area √ 2 × die area die yield = (1 + (defects per unit area × die area)/α)-αCSE477 L02 Design Metrics.11 Irwin&Vijay, PSU, 2003Yield Example Examplez wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2, α = 3 (measure of manufacturing process complexity)z 252 dies/wafer (remember, wafers round & dies square)z die yield of 16%z 252 x 16% = only 40 dies/wafer die yield ! Die cost is strong function of die areaz proportional to the third or fourth power of the die areaCSE477 L02 Design Metrics.12 Irwin&Vijay, PSU, 2003Examples of Cost Metrics (circa 1994)Chip Metal layersLine widthWafer costDefects/cm2Area (mm2)Dies/waferYield Die cost386DX 2 0.90 $900 1.0 43 360 71% $4486DX2 3 0.80 $1200 1.0 81 181 54% $12PowerPC 6014 0.80 $1700 1.3 121 115 28% $53HP PA 71003 0.80 $1300 1.0 196 66 27% $73DEC Alpha3 0.70 $1500 1.2 234 53 19% $149Super SPARC3 0.70 $1700 1.6 256 48 13% $272Pentium 3 0.80 $1500 1.5 296 40 9% $417CSE477 L02 Design Metrics.13 Irwin&Vijay, PSU, 2003ReliabilityNoise in Digital Integrated Circuits Noise – unwanted variations of voltages and currents at the logic nodesv(t)i(t) From two wires placed side by sidez capacitive coupling- voltage change on one wire can influence signal on the neighboring wire- cross talkz inductive coupling- current change on one wire can influence signal on the neighboring wireVDDFrom noise on the power and ground supply railsz can influence signal levels in the gateCSE477 L02 Design Metrics.14 Irwin&Vijay, PSU, 2003Example of Capacitive Coupling Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scaleCrosstalk vs.