CSE477VLSI Digital CircuitsFall 2003 Lecture 03: MOS TransistorCourse AdministrationReview: Fundamental Design MetricsReview: Reverse Bias DiodeReview: Design Abstraction LevelsThe MOS TransistorThe NMOS Transistor Cross SectionSwitch Model of NMOS TransistorSwitch Model of PMOS TransistorThreshold Voltage ConceptThe Threshold VoltageThe Body EffectTransistor in Linear ModeVoltage-Current Relation: Linear ModeTransistor in Saturation ModeVoltage-Current Relation: Saturation ModeCurrent DeterminatesLong Channel I-V Plot (NMOS)Long Channel I-V Plot (NMOS)Short Channel EffectsVoltage-Current Relation: Velocity SaturationVelocity Saturation EffectsShort Channel I-V Plot (NMOS)MOS ID-VGS CharacteristicsShort Channel I-V Plot (PMOS)The MOS Current-Source ModelOther (Submicon) MOS Transistor ConcernsSubthreshold ConductanceSubthreshold ID vs VGSSubthreshold ID vs VDSThreshold VariationsDIBLNext Time: The CMOS InverterNext Lecture and RemindersCSE477 L03 MOS Transistor.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 03: MOS TransistorMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L03 MOS Transistor.2 Irwin&Vijay, PSU, 2003Course Administration Instructor: Mary Jane [email protected]/~mji227 Pond LabOffice Hrs: T 16:00-17:00 & W 9:30-10:45 TA: Feihui Li Greg [email protected]@cse.psu.edu128 Hammond 226 Pond LabOffice Hrs: TBD TBD Labs: Accounts on 101 Pond Lab machines URL: www.cse.psu.edu/~cg477 Text: Digital Integrated Circuits, 2ndEdition Rabaey et. al., ©2003 Slides: pdf on the course web page after lectureCSE477 L03 MOS Transistor.3 Irwin&Vijay, PSU, 2003Review: Fundamental Design Metrics Functionalityz Found On First Spin ICs/ASICs:- Functional Logic Error ###################### 43%- Analog Tuning Issue ########## 20%- Signal Integrity Issue ######### 17%- Clock Scheme Error ####### 14%- Reliability Issue ###### 12%- Mixed Signal Problem ##### 11%- Uses Too Much Power ##### 11%- Has Path(s) Too Slow ##### 10%- Has Path(s) Too Fast ##### 10%- IR Drop Issues #### 7%- Firmware Error ## 4%- Other Problem # 3%- Overall 61% of New ICs/ASICs Require At Least One Re-Spin- Source: Aart de Geus, Chairman & CEO of Synopsys Costs (NRE (fixed) and RE (variable) costs) Reliability, robustness Performance (speed (delay) and power consumption) Time-to-marketCSE477 L03 MOS Transistor.4 Irwin&Vijay, PSU, 2003Review: Reverse Bias Diode The ideal diode equation (for both forward and reverse-bias conditions) isID= IS(eVD/ φT –1)where VDis the voltage applied to the junctionz a forward-bias lowers the potential barrier allowingcarriers to flow across the diode junctionz a reverse-bias raises the potential barrier and the diode becomes nonconductingφT= kT/q = 26mV at 300KISis the saturation current of the diode+-VD-0.50.51.52.5-1 -0.75 -0.5 -0.25 0 0.25 0.5 0.75 1ID(mA)VD(V)CSE477 L03 MOS Transistor.5 Irwin&Vijay, PSU, 2003Review: Design Abstraction LevelsSYSTEMGATECIRCUITVoutVinCIRCUITVoutVinMODULE+DEVICEn+SDn+GCSE477 L03 MOS Transistor.6 Irwin&Vijay, PSU, 2003The MOS TransistorPolysiliconAluminumCSE477 L03 MOS Transistor.7 Irwin&Vijay, PSU, 2003The NMOS Transistor Cross Sectionn areas have been doped with donor ions (arsenic) of concentration ND- electrons are the majority carriers p areas have been doped with acceptorions (boron) of concentration NA- holes are the majority carriers Gate oxiden+Source Drainp substrateBulk (Body)p+ stopperField-Oxide(SiO2)n+PolysiliconGateLWCSE477 L03 MOS Transistor.8 Irwin&Vijay, PSU, 2003Switch Model of NMOS TransistorGate| VGS |Source(of carriers)Drain(of carriers)Closed (on) (Gate = ‘1’)RonOpen (off) (Gate = ‘0’)| VGS | < | VT|| VGS | > | VT|CSE477 L03 MOS Transistor.9 Irwin&Vijay, PSU, 2003Switch Model of PMOS TransistorGateSource(of carriers)Drain(of carriers)| VGS |Open (off) (Gate = ‘1’)Closed (on) (Gate = ‘0’)Ron| VGS | > | VDD–| VT | | | VGS | < | VDD–|VT| |CSE477 L03 MOS Transistor.10 Irwin&Vijay, PSU, 2003Threshold Voltage ConceptGDSp substrateVGS +-n+n+depletion regionn channelBThe value of VGSwhere strong inversion occurs is called the threshold voltage, VTCSE477 L03 MOS Transistor.11 Irwin&Vijay, PSU, 2003The Threshold VoltageVT= VT0+ γ(√|-2φF+ VSB| - √|-2φF|)whereVT0 is the threshold voltage at VSB= 0 and is mostly a function of the manufacturing processz Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc.VSBis the source-bulk voltageφF= -φTln(NA/ni) is the Fermi potential (φT= kT/q = 26mV at 300K is the thermal voltage; NAis the acceptor ion concentration; ni≈ 1.5x1010cm-3at 300K is the intrinsic carrier concentration in pure silicon)γ = √(2qεsiNA)/Coxis the body-effect coefficient (impact of changes in VSB) (εsi=1.053x10-10F/m is the permittivity of silicon; Cox= εox/toxis the gate oxide capacitance with εox=3.5x10-11F/m)CSE477 L03 MOS Transistor.12 Irwin&Vijay, PSU, 2003The Body Effect0.40.450.50.550.60.650.70.750.80.850.9-2.5 -2 -1.5 -1 -0.5 0VBS(V)VT(V)z VSBis the substrate bias voltage (normally positive for n-channel devices with the body tied to ground)z A negative bias causes VTto increase from 0.45V to 0.85VCSE477 L03 MOS Transistor.13 Irwin&Vijay, PSU, 2003Transistor in Linear ModeAssuming VGS> VTSDBGn+n+VGSVDSIDxV(x)-+The current is a linear function of both VGSand VDSCSE477 L03 MOS Transistor.14 Irwin&Vijay, PSU, 2003Voltage-Current Relation: Linear ModeFor long-channel devices (L > 0.25 micron) When VDS≤ VGS–VTID= k’nW/L [(VGS–VT)VDS–VDS2/2]wherek’n= µnCox= µnεox/tox= is the process transconductance parameter (µnis the carrier mobility (m2/Vsec))kn= k’nW/L is the gain factor of the deviceFor small VDS, there is a linear dependence between VDSand ID, hence the name resistive or linear regionCSE477 L03 MOS Transistor.15 Irwin&Vijay, PSU, 2003Transistor in Saturation ModeAssuming VGS > VTSDBGVGSVDS > VGS-VTIDVGS-VT-+n+ n+Pinch-offVDSThe current remains constant (transistor saturates)CSE477 L03 MOS Transistor.16 Irwin&Vijay, PSU, 2003Voltage-Current Relation: Saturation ModeFor long channel devices When VDS≥ VGS–VTID’ = k’n/2 W/L [(VGS–VT) 2]since the voltage