CSE477 L17 Dynamic Sequential Circuits.1 Irwin&Vijay, PSU, 2001CSE477VLSI Digital CircuitsFall 2001Lecture 17: Dynamic Sequential Circuitswww.cse.psu.edu/~cg477[Adapted in part from Rabaey’s Digital Integrated Circuits, ©Prentice Hall, 1995]CSE477 L17 Dynamic Sequential Circuits.2 Irwin&Vijay, PSU, 2001You spend all this time designing one machine and it’s only a hot box for two years, and it has all the useful life of a washing machine.The Soul of a New Machine, Kidder, pg. 239CSE477 L17 Dynamic Sequential Circuits.3 Irwin&Vijay, PSU, 2001Review: Sequential Definitionsq Static versus dynamic storagel static have positive feedback (regeneration) with an internal connection between the output and the inputl dynamic store state on parasitic capacitors so only hold the state for a period of time (milliseconds)l dynamic are simpler, higher speed, lower powerq Latch versus flipflopl latches are level sensitive with two modes: transparent - inputs are passed to Q and hold - output stablel fliplflops are edge sensitive that only sample the inputs on a clock transitionCSE477 L17 Dynamic Sequential Circuits.4 Irwin&Vijay, PSU, 2001Review: Timing MetricsclockInOutdatastableoutputstabletsetuptholdtpFFoutputstabletimetimetimeCSE477 L17 Dynamic Sequential Circuits.5 Irwin&Vijay, PSU, 2001Review: System Timing ConstraintsCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsT ≥ tpFF+ tpcomb+ tsetuptcdreg+ tcdlogic≥ tholdTCSE477 L17 Dynamic Sequential Circuits.6 Irwin&Vijay, PSU, 2001Dynamic ET FlipflopT1T2I1I2QQMDC1C2!clkclkclk!clk!clkclkCSE477 L17 Dynamic Sequential Circuits.7 Irwin&Vijay, PSU, 2001Dynamic ET FlipflopT1T2I1I2QQMDC1C2!clkclkclk!clk!clkclkmaster transparentslave holdmaster holdslave transparentCSE477 L17 Dynamic Sequential Circuits.8 Irwin&Vijay, PSU, 2001Dynamic ET FF Race ConditionsT1T2I1I2QQMDC1C2!clkclkclk!clk!clkclk0-0 overlap race conditiontoverlap0-0< tT1+tI1+ tT21-1 overlap race conditionthold> toverlap1-1CSE477 L17 Dynamic Sequential Circuits.9 Irwin&Vijay, PSU, 2001Dynamic Two-Phase ET FFclk2clk1tnon_overlapT1T2I1I2QQMDC1C2clk1!clk1clk2!clk2CSE477 L17 Dynamic Sequential Circuits.10 Irwin&Vijay, PSU, 2001C2MOS MS ET Flipflopclk!clk!clkclkQMC1C2QDM1M3M4M2M6M8M7M5Master Slave!clkclkCSE477 L17 Dynamic Sequential Circuits.11 Irwin&Vijay, PSU, 2001C2MOS MS ET Flipflopclk!clk!clkclkQMC1C2QDM1M3M4M2M6M8M7M5Master Slave!clkclkmaster transparentslave holdmaster holdslave transparent ononoffoffononoffoffCSE477 L17 Dynamic Sequential Circuits.12 Irwin&Vijay, PSU, 2001C2MOS FF 0-0 Overlap Case0 0QMC1C2QDM1M4M2M6M8M5!clkclk!clkclkCSE477 L17 Dynamic Sequential Circuits.13 Irwin&Vijay, PSU, 2001C2MOS FF 1-1 Overlap Case1 1QMC1C2QDM1M2M6M5!clkclkM3M7!clkclkCSE477 L17 Dynamic Sequential Circuits.14 Irwin&Vijay, PSU, 2001C2MOS Transient Response-0.500.511.522.530 2 4 6 8QM(3)Q(3)Q(0.1)Time (nsec)VoltsCSE477 L17 Dynamic Sequential Circuits.15 Irwin&Vijay, PSU, 2001True Single Phase Clocked (TSPC) Latchesclk clkDQPositive LatchNegative Latchtransparent when clk = 1hold when clk = 0clk clkDQhold when clk = 1transparent when clk = 0CSE477 L17 Dynamic Sequential Circuits.16 Irwin&Vijay, PSU, 2001Embedding Logic in TSPC Latchclk clkInQPUNPDNclk clkAQBBACSE477 L17 Dynamic Sequential Circuits.17 Irwin&Vijay, PSU, 2001True Single Phase ET FFclkclk clkDMaster SlaveclkclkQQMCSE477 L17 Dynamic Sequential Circuits.18 Irwin&Vijay, PSU, 2001True Single Phase ET FFclkmaster holdslave transparentclk clkDMaster SlaveclkclkQQMmaster transparentslave holdononoffoffononoffoffon onoffoffCSE477 L17 Dynamic Sequential Circuits.19 Irwin&Vijay, PSU, 2001Split-Output TSPC LatchesclkDQPositive LatchNegative Latchtransparent when clk = 1hold when clk = 0clkDQhold when clk = 1transparent when clk = 0AACSE477 L17 Dynamic Sequential Circuits.20 Irwin&Vijay, PSU, 2001Split-Output TSPC ET FFclkDQclkCSE477 L17 Dynamic Sequential Circuits.21 Irwin&Vijay, PSU, 2001Simplified TSPC ET FFclkD clkQclkclkXYM1M2M3M6M5M4M7M8M9clkmaster holdslave transparentmaster transparentslave holdononoffoff→ 1→ !Donoffonoff→ D→ DCSE477 L17 Dynamic Sequential Circuits.22 Irwin&Vijay, PSU, 2001Transistor Sizing Issues in TSPC01230 0.2 0.4 0.6 0.8 1Time (nsec)Voltsclk!QorigQorig!QmodQmodTransistor sizingOriginal widthM4, M5= 0.5µmM7, M8= 2µmModified widthM4, M5= 1µmM7, M8= 1µmCSE477 L17 Dynamic Sequential Circuits.23 Irwin&Vijay, PSU, 2001Pulsed FF (AMD-K6)q Pulse registers - a short pulse (glitch clock) is generated locally from the rising (or falling) edge of the clock and is used as the clock input to the latchl race conditions are avoided by keeping the transparent mode timevery short (during the pulse only)l advantage is reduced clock load; disadvantage is substantial increase in verification complexityclkDQM1M2M3M4M5M6P1P2P3X!clkd0ONVddOFFOFF11 0ON1/0ON/OFF0/VddON/OFF1/00OFF11OFFONONONCSE477 L17 Dynamic Sequential Circuits.24 Irwin&Vijay, PSU, 2001Sense Amp FF (StrongArm SA100)clkDQ!QM1M2M3M5M6M4M9M7M8M10q Sense amplifier (circuits that accept small swing input signals and amplify them to full rail-to-rail signals) flipflopsl advantages are reduced clock load and that it can be used as a receiver for reduced swing differential buses00111110101CSE477 L17 Dynamic Sequential Circuits.25 Irwin&Vijay, PSU, 2001Flipflop Comparison Chart203 (clk)SenseAmpSA 100195 (clk)DynamicAMD K6102 (clk)DynamicS-O TSPC3tpinvtpinv114 (clk)DynamicTSPC2tpinv+tptxtpinv+tptxtpFF84 (clk-!clk)DynamicC2MOSto1-1tptx84 (clk-!clk)DynamicT-gate168 (clk1-clk2)Ps-Static2-phase168 (clk-!clk)StaticPowerPC03tpinv+tptx208 (clk-!clk)StaticMuxtholdtset-up#tr#clk ldTypeNameCSE477 L17 Dynamic Sequential Circuits.26 Irwin&Vijay, PSU, 2001Pipelining using C2MOSclk!clk!clkclkC1C2OutFM1M3M4M2M6M8M7M5InGclk!clkM1M3M4M2C3NORA LogicWhat are the constraints on F and G?CSE477 L17 Dynamic Sequential Circuits.27 Irwin&Vijay, PSU, 2001Example 1φφVDDφφVDDVDDNumber of a static inversions should be evenCSE477 L17 Dynamic Sequential Circuits.28 Irwin&Vijay, PSU, 2001NORA CMOS Modules φφVDDVDDPDNφIn1In2In3φVDDPUNφφOutφφVDDOutVDDPDNφIn1In2In3φVDDIn4In4VDD(a) φ-module(b) φ-moduleCombinational logic LatchCSE477 L17 Dynamic Sequential Circuits.29 Irwin&Vijay, PSU, 2001Next Lecture and Remindersq Next lecturel Datapath design; RCAs - Reading assignment – Rabaey, 7.1 through 7.3.2q Remindersl Evening exam scheduled- Tuesday November 6, 8:15 to 10:15