CSE477VLSI Digital CircuitsFall 2003 Lecture 17: Static Sequential CircuitsReview: How to Choose a Logic StyleSequential LogicTiming MetricsSystem Timing ConstraintsStatic vs Dynamic StorageLatches vs FlipflopsPositive and Negative LatchesReview: The Regenerative PropertyBistable CircuitsReview (from CSE 271): SR LatchReview (from CSE 271): Clocked D LatchMUX Based LatchesTG MUX Based Latch ImplementationPT MUX Based Latch ImplementationLatch Race ProblemMaster Slave Based ET FlipflopMS ET ImplementationMS ET ImplementationMS ET Timing PropertiesMS ET Timing PropertiesSet-up Time SimulationSet-up Time SimulationPropagation Delay SimulationPower PC FlipflopPower PC FlipflopReduced Load MS ET FFNon-Ideal ClocksExample of Clock Skew ProblemsPseudostatic Two-Phase ET FFTwo Phase Clock GeneratorRatioed CMOS Clocked SR LatchRatioed CMOS Clocked SR LatchSizing IssuesTransient Response6 Transistor CMOS SR LatchNext Lecture and RemindersCSE477 L17 Static Sequential Logic.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 17: Static Sequential CircuitsMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L17 Static Sequential Logic.2 Irwin&Vijay, PSU, 2003Review: How to Choose a Logic Style Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing4-input NANDStyle # Trans Ease Ratioed? Delay PowerComp Static 8 124no 33CPL* 12 + 2 no 4132 + clkdomino 6 + 2 no 2DCVSL* 10 4yes 1* Dual Rail Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling.CSE477 L17 Static Sequential Logic.3 Irwin&Vijay, PSU, 2003A time was probably coming when components would operate so quickly that the distance that signals had to travel would intimately affect the speed of most commercial computers. Then miniaturization and speed would become more nearly synonymous.The Soul of a New Machine, Kidder, pg. 160CSE477 L17 Static Sequential Logic.4 Irwin&Vijay, PSU, 2003Sequential LogicCombinationalLogicOutputsInputsStateRegistersNextStateCurrentStateclockCSE477 L17 Static Sequential Logic.5 Irwin&Vijay, PSU, 2003Timing MetricsclockInOutdatastableoutputstableoutputstabletimetimetimeclockDQInOuttsutholdtc-qCSE477 L17 Static Sequential Logic.6 Irwin&Vijay, PSU, 2003System Timing ConstraintsCombinationalLogicclockInputs OutputsStateRegistersNextStateCurrentStateT (clock period)tcdreg+ tcdlogic≥ tholdT ≥ tc-q+ tplogic+ tsuCSE477 L17 Static Sequential Logic.7 Irwin&Vijay, PSU, 2003Static vs Dynamic Storage Static storagez preserve state as long as the power is onz have positive feedback (regeneration) with an internal connection between the output and the inputz useful when updates are infrequent (clock gating) Dynamic storagez store state on parasitic capacitorsz only hold state for short periods of time (milliseconds)z require periodic refreshz usually simpler, so higher speed and lower powerCSE477 L17 Static Sequential Logic.8 Irwin&Vijay, PSU, 2003Latches vs Flipflops Latchesz level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent modez input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode Flipflops (edge-triggered)z edge sensitive circuits that sample the inputs on a clock transition- positive edge-triggered: 0 → 1- negative edge-triggered: 1 → 0z built using latches (e.g., master-slave flipflops)CSE477 L17 Static Sequential Logic.9 Irwin&Vijay, PSU, 2003Positive and Negative LatchesclockDQInOutclockDQInOutclk clkOutIn InOutCSE477 L17 Static Sequential Logic.10 Irwin&Vijay, PSU, 2003Review: The Regenerative PropertyVi1Vo2Vi2Vo1cascaded invertersVi2 = Vo1If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point.ABCVi1 = Vo2CSE477 L17 Static Sequential Logic.11 Irwin&Vijay, PSU, 2003Bistable CircuitsVi1 The cross-coupling of two inverters results in a bistablecircuit (a circuit with two stable states)Vi2 Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1z done by applying a trigger pulse at Vi1or Vi2z the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter) Two approaches usedz cutting the feedback loop (mux based latch)z overpowering the feedback loop (as used in SRAMs)CSE477 L17 Static Sequential Logic.12 Irwin&Vijay, PSU, 2003Review (from CSE 271): SR LatchSRQ!Q00Q!Qmemory1010 set0101 reset1100disallowedS!QQRCSE477 L17 Static Sequential Logic.13 Irwin&Vijay, PSU, 2003Review (from CSE 271): Clocked D LatchDQ!QclockclockD LatchQDtransparent modeclockhold modeCSE477 L17 Static Sequential Logic.14 Irwin&Vijay, PSU, 2003MUX Based LatchesChange the stored value by cutting the feedback loopfeedbackclk10feedbackclk01Q QD DNegative Latch Positive LatchQ = !clk & Q | clk & DQ = clk & Q | !clk & Dtransparent when the clock is lowtransparent when the clock is highCSE477 L17 Static Sequential Logic.15 Irwin&Vijay, PSU, 2003TG MUX Based Latch ImplementationQDclkclk!clk!clkclkinput sampled(transparent mode)feedback(hold mode)clkD LatchQDCSE477 L17 Static Sequential Logic.16 Irwin&Vijay, PSU, 2003PT MUX Based Latch Implementation!QclkQD!clkclkinput sampled(transparent mode)feedback(hold mode)!clk Reduced area and clock load, but a threshold drop at output of pass transistors so reduced noise margins and performanceCSE477 L17 Static Sequential Logic.17 Irwin&Vijay, PSU, 2003Latch Race ProblemCombinationalLogicclkStateRegistersclkBB’Two-sided clock constraintT ≥ tc-q+ tplogic+ tsuThigh< tc-q+ tcdlogicBWhich value of B is stored?CSE477 L17 Static Sequential Logic.18 Irwin&Vijay, PSU, 2003Master Slave Based ET FlipflopclockD FFQDQM1D010QMclk01QSlaveQclk10DMasterSlaveMasterclkDclk = 0 transparent holdQMclk = 0→1 hold transparentQCSE477 L17 Static Sequential Logic.19 Irwin&Vijay, PSU, 2003MS ET ImplementationSlaveMasterQDclkQMI1I2I3I4I5I6T2T1T3T4!clkclkCSE477 L17 Static Sequential Logic.20 Irwin&Vijay, PSU, 2003MS ET ImplementationSlaveMasterQDclkQMI1I2I3I4I5I6T2T1T3T4!clkclkmaster