CSE477 L01 Introduction.1 Irwin&Vijay, PSU, 2001CSE477VLSI Digital CircuitsFall 2001Lecture 01: IntroductionVijay Narayanan (www.cse.psu.edu/~vijay)www.cse.psu.edu/~cg477[Adapted in part from Rabaey’s Digital Integrated Circuits]CSE477 L01 Introduction.2 Irwin&Vijay, PSU, 2001Course Contentsq Introduction to digital integrated circuitsl CMOS devices and manufacturing technology. CMOS logic structures and layout. Propagation delay, power dissipation, noise margins. Combinational (e.g., arithmetic) and sequential circuit design. Memory design.q Course goalsl Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliabilityq Course prerequisitesl EE 310. Electronic Circuit Designl CSE 471. Logic Design of Digital SystemsCSE477 L01 Introduction.3 Irwin&Vijay, PSU, 2001Course Administrationq Instructor: Vijaykrishnan [email protected]/~vijay229 Pond LabOffice Hrs: T 4-5pm: and W 1-2pmq TA: Xiheng (David) [email protected] Labs: Accounts on 101 Pond Lab machinesq URL: www.cse.psu.edu/~cg477q Texts: Digital Integrated Circuits, Rabaey, 1996Class notes – on the webCSE477 L01 Introduction.4 Irwin&Vijay, PSU, 2001Grading Informationq Grade determinantsl Midterm Exams ~15% each- October 4 and November 6 (20:15-22:15) - Check for updatesl Final Exam ~20%- Dec 14th, 12:20-2:10pm, Location TBDl Homeworks/Lab Assignments (5) ~20%- Due at the beginning of class (or, if submitted electronically, by 17:00 on the due date). No late assignments will be accepted.l In class pop quiz ~ 5%l Design Project (teams of ~2) ~25%q Please let me know about exam conflicts ASAPq Grades will be posted on the course homepagel Must submit email request for change of grade after discussions with the TA (Homeworks/Lab Assignments) or instructor (Exams)l Dec 7thdeadline for filing grade corrections; no requests for grade changes/updates will be accepted after this dateCSE477 L01 Introduction.5 Irwin&Vijay, PSU, 2001Background from CSE471 and EE310q Basic circuit theoryl resistance, capacitance, inductancel MOS gate characteristicsq Hardware description languagel VHDL or verilogq Use of modern EDA toolsl simulation, synthesis, validation (Synopsys)l schematic capture tools (LogicWorks)q Logic designl logical minimization, FSMs, component designCSE477 L01 Introduction.6 Irwin&Vijay, PSU, 2001Course Structureq Design and tool intensive classl Micromagic (MMI) “max” and “sue” for layout- Online documentation and tutorialsl HSPICE for circuit simulationl IRSIM for functional simulationq Lectures:l 2 weeks on the CMOS inverter l 3 weeks on static and dynamic CMOS gatesl 2 weeks on C, R, and L effects l 2 week on sequential CMOS circuits l 2 weeks on design of datapath structuresl 2 weeks on memory designl 1 week on design for test, margining, scaling, trends l 2 evening exams (instead of 2 cancelled classes)CSE477 L01 Introduction.7 Irwin&Vijay, PSU, 2001“Executives might make the final decisions about what would be produced, but engineers would provide most of the ideas for new products. After all, engineers were the people who really knew the state of the art and who were therefore best equipped to prophesy changes in it.”The Soul of a New Machine, Kidder, pg 35CSE477 L01 Introduction.8 Irwin&Vijay, PSU, 2001Transistor Revolutionq Transistor –Bardeen (Bell Labs) in 1947q Bipolar transistor – Schockley in 1949q First bipolar digital logic gate – Harris in 1956q First monolithic IC – Jack Kilby in 1959q First commercial IC logic gates – Fairchild 1960q TTL – 1962 into the 1990’sq ECL – 1974 into the 1980’sCSE477 L01 Introduction.9 Irwin&Vijay, PSU, 2001MOSFET Technologyq MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935q CMOS – 1960’s, but plagued with manufacturing problemsq PMOS in 1960’s (calculators)q NMOS in 1970’s (4004, 8080) – for speedq CMOS in 1980’s – preferred MOSFET technology because of power benefitsq BiCMOS, Gallium-Arsenide, Silicon-Germaniumq SOI, Copper-Low K, …CSE477 L01 Introduction.10 Irwin&Vijay, PSU, 2001Moore’s Lawq Gordon Moore predicted that the number of transistors that can be integrated on a die would grow exponentially with time.q Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s.q 2300 transistors (Intel 4004) - 1971 q 42 Million (Intel P4) - 2001CSE477 L01 Introduction.11 Irwin&Vijay, PSU, 2001Moore’s Law’70 ’73 ’76 ’79 ’82 ’85 ’88 ’91 ’94 '97 2000’70 ’73 ’76 ’79 ’82 ’85 ’88 ’91 ’94 '97 2000Source: Intel Source: Intel TransistorsTransistorsPer DiePer Die1010881010771010661010551010441010331010221010111010001K1K4K4K16K16K64K64K256K256K1M1M16M16M4M4M64M64M4004400480808080808680868028680286i386™i386™i486™i486™PentiumPentium®®MemoryMemoryMicroprocessorMicroprocessorPentiumPentium® ® IIIIII256M256MPentiumPentium®®ProProPentiumPentium® ® IIIIMoore’s Law: transistors/chip doubles every 1.5 yearsCause: shrinking feature size & growing die sizeCSE477 L01 Introduction.12 Irwin&Vijay, PSU, 2001Evolution of Intel Processorsq Doubling of transistor density every 30 monthsq Increasing die sizes, allowed by l Increasing Wafer Sizeq ⇒ Doubling of transistors every 18 monthsTechOld µArchmm (linear)New µArchmm (linear)RatioRatio1.0µi386C 6.5 i486 11.5 3.10.7µi486C 9.5 Pentium® proc17 3.20.5µPentium® proc12.2 Pentium Pro®proc17.3 2.10.18µPentium III®proc10.3 Next Gen ? 2--3Implications: (in the same technology)1. New µArch ~ 2-3X die area of the last µArch2. Provides 1.5-1.7X integer performance of the last µArchCSE477 L01 Introduction.13 Irwin&Vijay, PSU, 2001Intel 4004 Micro-Processor (1971)CSE477 L01 Introduction.14 Irwin&Vijay, PSU, 2001Intel Pentium (II) Microprocessor (1997)CSE477 L01 Introduction.15 Irwin&Vijay, PSU, 2001642561,0004,00016,00064,000256,0001,000,0004,000,00016,000,00064,000,000101001000100001000001000000100000001000000001980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010Year of introductionKbit capacity/chipEvolution in DRAM Chip Capacity1.6-2.4 µm1.0-1.2 µm0.7-0.8 µm0.5-0.6 µm0.35-0.4 µm0.18-0.25 µm0.13 µm0.1 µm0.07 µmhuman memoryhuman DNAencyclopedia2 hrs CD audio30 sec HDTVbookpageMemory IC(bits/chip)4 times every 3 yearsCSE477 L01 Introduction.16 Irwin&Vijay, PSU, 2001Clock Frequency Trends101001,00010,000MhzFrequency doubles each