CSE477VLSI Digital CircuitsFall 2003 Lecture 04: CMOS Inverter (static view)Review: Design Abstraction LevelsReview: The MOS TransistorCMOS Inverter: A First LookCMOS Inverter: Steady State ResponseCMOS PropertiesReview: Short Channel I-V Plot (NMOS)Review: Short Channel I-V Plot (PMOS)Transforming PMOS I-V LinesCMOS Inverter Load LinesCMOS Inverter VTCCMOS Inverter VTCCMOS Inverter: Switch Model of Dynamic BehaviorCMOS Inverter: Switch Model of Dynamic BehaviorRelative Transistor SizingSwitching ThresholdSwitch Threshold ExampleSwitch Threshold ExampleSimulated Inverter VMNoise Margins Determining VIH and VILCMOS Inverter VTC from SimulationGain DeterminatesImpact of Process Variation on VTC CurveScaling the Supply VoltageNext Time: CMOS Inverter max LayoutNext Lecture and RemindersCSE477 L04 CMOS Inverter.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 04: CMOS Inverter (static view)Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L04 CMOS Inverter.2 Irwin&Vijay, PSU, 2003Review: Design Abstraction LevelsSYSTEMGATECIRCUITVoutVinCIRCUITVoutVinMODULE+DEVICEn+SDn+GCSE477 L04 CMOS Inverter.3 Irwin&Vijay, PSU, 2003Review: The MOS TransistorGate oxiden+Source Drainp substrateField-Oxide(SiO2)p+ stoppern+PolysiliconGateLWBulk (Body)CSE477 L04 CMOS Inverter.4 Irwin&Vijay, PSU, 2003CMOS Inverter: A First LookVDDCLVinVoutCSE477 L04 CMOS Inverter.5 Irwin&Vijay, PSU, 2003CMOS Inverter: Steady State ResponseVOL= 0VOH= VDDVM= f(Rn, Rp)VDDVDDRnVout= 0Vin= VDDRpVout= 1Vin= 0CSE477 L04 CMOS Inverter.6 Irwin&Vijay, PSU, 2003CMOS Properties Full rail-to-rail swing ⇒ high noise marginsz Logic levels not dependent upon the relative device sizes ⇒transistors can be minimum size ⇒ ratioless Always a path to Vddor GND in steady state ⇒ low output impedance (output resistance in kΩ range) ⇒large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) ⇒ nearly zero steady-state input current No direct path steady-state between power and ground ⇒ no static power dissipation Propagation delay function of load capacitance and resistance of transistorsCSE477 L04 CMOS Inverter.7 Irwin&Vijay, PSU, 2003Review: Short Channel I-V Plot (NMOS)00.511.522.500.511.522.5ID(A)VDS(V)X 10-4VGS= 1.0VVGS= 1.5VVGS= 2.0VVGS= 2.5VLineardependenceNMOS transistor, 0.25um, Ld= 0.25um, W/L = 1.5, VDD= 2.5V, VT= 0.4VCSE477 L04 CMOS Inverter.8 Irwin&Vijay, PSU, 2003Review: Short Channel I-V Plot (PMOS)z All polarities of all voltages and currents are reversed-1-0.8-0.6-0.4-0.200-1-2ID(A)VDS(V)X 10-4VGS= -1.0VVGS= -1.5VVGS= -2.0VVGS= -2.5VPMOS transistor, 0.25um, Ld= 0.25um, W/L = 1.5, VDD= 2.5V, VT= -0.4VCSE477 L04 CMOS Inverter.9 Irwin&Vijay, PSU, 2003Transforming PMOS I-V Linesz Want common coordinate set Vin, Vout, and IDnVoutIDnIDSp= -IDSnVGSn= Vin; VGSp= Vin-VDDVDSn= Vout; VDSp= Vout-VDDVGSp= -2.5VGSp= -1Mirror around x-axisVin= VDD+ VGSpIDn= -IDpVin= 1.5Vin= 0Vin= 1.5Vin= 0Horiz. shift over VDDVout= VDD+ VDSpCSE477 L04 CMOS Inverter.10 Irwin&Vijay, PSU, 2003CMOS Inverter Load Lines00.511.522.500.511.522.5Vout(V)X 10-4Vin= 1.0VVin= 1.5VVin= 2.0VVin= 2.5V0.25um, W/Ln= 1.5, W/Lp= 4.5, VDD= 2.5V, VTn= 0.4V, VTp= -0.4VVin= 0VVin= 0.5VVin= 1.0VVin= 1.5VVin= 0.5VVin= 2.0VVin= 2.5VVin= 2VVin= 1.5VVin= 1VVin= 0.5VVin= 0VPMOS NMOSIDn(A)CSE477 L04 CMOS Inverter.11 Irwin&Vijay, PSU, 2003CMOS Inverter VTC00.511.522.500.511.522.5Vin(V)Vout(V)CSE477 L04 CMOS Inverter.12 Irwin&Vijay, PSU, 2003CMOS Inverter VTC00.511.522.500.511.522.5Vin(V)Vout(V)NMOS offPMOS linearNMOS satPMOS linearNMOS satPMOS satNMOS linearPMOS satNMOS linearPMOS offCSE477 L04 CMOS Inverter.13 Irwin&Vijay, PSU, 2003CMOS Inverter: Switch Model of Dynamic BehaviorVDDRnVoutCLVin= VDDVDDRpVoutCLVin= 0CSE477 L04 CMOS Inverter.14 Irwin&Vijay, PSU, 2003CMOS Inverter: Switch Model of Dynamic BehaviorVDDRnVoutCLVin= VDDVDDRpVoutCLVin= 0z Gate response time is determined by the time to charge CLthrough Rp(discharge CLthrough Rn)CSE477 L04 CMOS Inverter.15 Irwin&Vijay, PSU, 2003Relative Transistor Sizing  When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section toz maximize the noise margins andz obtain symmetrical characteristicsCSE477 L04 CMOS Inverter.16 Irwin&Vijay, PSU, 2003Switching Threshold VMwhere Vin= Vout(both PMOS and NMOS in saturation since VDS= VGS)VM≈ rVDD/(1 + r) where r = kpVDSATp/knVDSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Want VM= VDD/2 (to have comparable high and low noise margins), so want r ≈ 1 (W/L)pkn’VDSATn(VM-VTn-VDSATn/2)(W/L)nkp’VDSATp(VDD-VM+VTp+VDSATp/2)=CSE477 L04 CMOS Inverter.17 Irwin&Vijay, PSU, 2003Switch Threshold Example In our generic 0.25 micron CMOS process, using the process parameters from slide L03.26, a VDD= 2.5V, and a 1.5 size NMOS device (W/L)nVT0(V)γ(V0.5)VDSAT(V) k’(A/V2)λ(V-1)NMOS 0.43 0.4 0.63 115 x 10-60.06PMOS -0.4 -0.4 -1 -30 x 10-6-0.1(W/L)p(W/L)n =CSE477 L04 CMOS Inverter.18 Irwin&Vijay, PSU, 2003Switch Threshold Example In our generic 0.25 micron CMOS process, using the process parameters from slide L03.26, a VDD= 2.5V, and a 1.5 size NMOS device (W/L)nVT0(V)γ(V0.5)VDSAT(V) k’(A/V2)λ(V-1)NMOS 0.43 0.4 0.63 115 x 10-60.06PMOS -0.4 -0.4 -1 -30 x 10-6-0.1(W/L)p115 x 10-60.63 (1.25 – 0.43 – 0.63/2) (W/L)n -30 x 10-6 -1.0 (1.25 – 0.4 – 1.0/2)=xx= 3.5(W/L)p= 3.5 x 1.5 = 5.25 for a VMof 1.25VCSE477 L04 CMOS Inverter.19 Irwin&Vijay, PSU, 2003Simulated Inverter VM0.80.911.11.21.31.41.50110(W/L)p/(W/L)n VMis relatively insensitive to variations in device ratioz setting the ratio to 3, 2.5 and 2 gives VM’s of 1.22V, 1.18V, and 1.13V Increasing the width of the PMOS moves VMtowards VDD Increasing the width of the NMOS moves VMtoward GND.1Note: x-axis is semilog~3.4VM(V)CSE477 L04 CMOS Inverter.20 Irwin&Vijay, PSU, 2003Noise Margins Determining VIHand VIL0123VIL VIHVinVOH= VDDVMVoutBy definition, VIHand VILare where dVout/dVin= -1 (= gain)VOL= GNDA piece-wise linear approximation of VTCNMH = VDD -VIHNML = VIL -GNDApproximating: VIH = VM -VM /gVIL = VM + (VDD -VM )/gSo high gain in the transition region is