CSE477VLSI Digital CircuitsFall 2003 Lecture 25: Peripheral Memory CircuitsReview: Read-Write Memories (RAMs)Review: 2D Memory BankPeripheral Memory CircuitryRow DecodersImplementing a Wide NOR FunctionSplit Row Two-Level 8x256 DecoderPass Transistor Based Column DecoderTree Based Column DecoderDecoder Complexity ComparisonsBit Line Precharge LogicSense AmplifiersClasses of Sense AmplifiersLatch Based Sense AmplifierAlpha Differential Amplifier/LatchRead/Write CircuitryApproaches to Memory TimingReliability and YieldRedundancy in the Memory StructureRedundancy and Error CorrectionSoft ErrorsNext Lecture and RemindersCSE477 L25 Memory Peripheral.1 Irwin&Vijay, PSU, 2003CSE477VLSI Digital CircuitsFall 2003Lecture 25: Peripheral Memory CircuitsMary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]CSE477 L25 Memory Peripheral.2 Irwin&Vijay, PSU, 2003Review: Read-Write Memories (RAMs) Static – SRAMz data is stored as long as supply is appliedz large cells (6 fets/cell) – so fewer bits/chipz fast – so used where speed is important (e.g., caches)z differential outputs (output BL and !BL) z use sense amps for performancez compatible with CMOS technology Dynamic – DRAMz periodic refresh required (every 1 to 4 ms) to compensate for the charge loss caused by leakagez small cells (1 to 3 fets/cell) – so more bits/chipz slower – so used for main memoriesz single ended output (output BL only)z need sense amps for correct operationz not typically compatible with CMOS technologyCSE477 L25 Memory Peripheral.3 Irwin&Vijay, PSU, 2003Review: 2D Memory BankRow DecoderRead PrechargeRead PrechargePrecharge CircuitPrecharge CircuitColumn DecoderSense AmpsColumn DecoderAN-1 …AiAi-1 …A0Write CircuitrySense AmpsWrite CircuitrydataCSE477 L25 Memory Peripheral.4 Irwin&Vijay, PSU, 2003Peripheral Memory Circuitry Row and column decoders Read bit line precharge logic Sense amplifiers Read/write circuitry Timing and control Speed Power consumption Area – pitch matchingCSE477 L25 Memory Peripheral.5 Irwin&Vijay, PSU, 2003Row Decoders Collection of 2Mcomplex logic gates organized in a regular, dense fashion (N)AND decoder for 8 address bitsWL(0) = !A7 & !A6 & !A5 & !A4 & !A3 & !A2 & !A1 & !A0…WL(255) = A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0 NOR decoder for 8 address bitsWL(0) = !(A7| A6| A5| A4| A3| A2| A1| A0)…WL(255) = !(!A7| !A6| !A5| !A4| !A3| !A2| !A1| !A0) Goals: Pitch matched, fast, low powerCSE477 L25 Memory Peripheral.6 Irwin&Vijay, PSU, 2003Implementing a Wide NOR Function Single stage 8x256 bit decoder (as in Lecture 22)z One 8 input NOR gate per row x 256 rows = 256 x (8+8) = 4,096z Pitch match and speed/power issues  Decompose logic into multiple levels!WL(0) = !(!(A7| A6) & !(A5| A4) & !(A3| A2) & !(A1| A0))z First level is the predecoder (for each pair of address bits, form Ai|Ai-1, Ai|!Ai-1, !Ai|Ai-1, and !Ai|!Ai-1) z Second level is the word line driver Predecoders reduce the number of transistors requiredz Four sets of four 2-bit NOR predecoders = 4 x 4 x (2+2) = 64z 256 word line drivers, each a four input NAND – 256 x (4+4) = 2,048- 4,096 vs 2,112 = almost a 50% savingsNumber of inputs to the gates driving the WLs is halved, so the propagation delay is reduced by a factor of ~4CSE477 L25 Memory Peripheral.7 Irwin&Vijay, PSU, 2003Split Row Two-Level 8x256 Decoder!(!A0 & !A1 & !A2). . .!(A0 &A1 &A2)!(!(!A0&!A1&!A2) | !(!A3&!A4&!A5) | !(!A6&!A7))*256WL255WL0*256WL255WL0Address<7:0>*8*8*8 *8 *4 Pitch matched Buffered word line driversCSE477 L25 Memory Peripheral.8 Irwin&Vijay, PSU, 2003Pass Transistor Based Column DecoderBL3BL2BL1BL0data_out2 input NOR decoderA1A0S3S2S1S0 Read: connect BLs to the Sense Amps (SA) Writes: drive one of the BLs low to write a 0 into the cellz Fast since there is only one transistor in the signal path. However, there is a large transistor count ( (K+1)2K+ 2 x 2K)z For K = 2 → 3 x 22(decoder) + 2 x 22 (PTs) = 12 + 8 = 20!BL3!BL2!BL1!BL0!data_outCSE477 L25 Memory Peripheral.9 Irwin&Vijay, PSU, 2003Tree Based Column DecoderBL3BL2BL1BL0A0!A0A1!A1data_out Number of transistors reduced to (2 x 2 x (2K-1))z for K = 2 → 2 x 2 x (22– 1) = 4 x 3 = 12 Delay increases quadratically with the number of sections (K) (so prohibitive for large decoders)z can fix with buffers, progressive sizing, combination of tree and pass transistor approaches!BL3!BL2!BL1!BL0!data_outCSE477 L25 Memory Peripheral.10 Irwin&Vijay, PSU, 2003Decoder Complexity Comparisons Consider a memory with 10b address and 8b dataConf. Data/Row Row Decoder Column Decoder1D 8b 10b = a 10x210decoder Single stage = 20,480 Two stage = 10,3202D 32b(32x256 core)8b = 8x28decoder Single stage = 4,096 T Two stage = 2,112 T2b = 2x22decoder PT = 76 T Tree = 96 T2D 64b(64x128 core)7b = 7x27decoder Single stage = 1,792 T Two stage = 1,072 T3b = 3x23decoder PT = 160 T Tree = 224 T2D 128b(128x64 core)6b = 6x26decoder Single stage = 768 T Two stage = 432 T4b = 4x24decoder PT = 336 T Tree = 480 TCSE477 L25 Memory Peripheral.11 Irwin&Vijay, PSU, 2003Bit Line Precharge Logic First step of a Read cycle is to precharge(PC) the bit lines to VDDz every differential signal in the memory must be equalized to the same voltage level before Read Turn off PC and enable the WLz the grounded PMOS load limits the bit line swing (speeding up the next precharge cycle)equalization transistor - speeds up equalization of the two bit lines by allowing the capacitance and pull-up device of the nondischarged bit line to assist in precharging the discharged line!PC!BLBLCSE477 L25 Memory Peripheral.12 Irwin&Vijay, PSU, 2003Sense Amplifiers Amplification – resolves data with small bit line swings (in some DRAMs required for proper functionality) Delay reduction – compensates for the limited drive capability of the memory cell to accelerate BL transitionSAinputoutputtp= ( C * ∆V ) / Iavlargesmallmake ∆ V as small as possible Power reduction – eliminates a large part of the power dissipation due to charging and discharging bit lines Signal restoration – for DRAMs, need to drive the bit lines full swing after sensing (read) to do data refreshCSE477 L25