CSE477 L10 Inverter Dynamic View.1 Irwin&Vijay, PSU, 2001CSE477VLSI Digital CircuitsFall 2001Lecture 10: Inverter, Dynamic ViewVijay Narayananwww.cse.psu.edu/~cg477[Adapted in part from Rabaey’s Digital Integrated Circuits, ©Prentice Hall, 1995]CSE477 L10 Inverter Dynamic View.2 Irwin&Vijay, PSU, 2001CMOS Inverter: DynamicVDDRnVout = 0Vin = VDDCLtpHL= f(Rn, CL)CSE477 L10 Inverter Dynamic View.3 Irwin&Vijay, PSU, 2001Review: Sources of CapacitanceVoutCwVinCDB2CDB1CGD12M2M1M4M3Vout2CG4CG3wiring capacitanceintrinsic MOS transistor capacitancesVout2Vinextrinsic MOS transistor capacitancesCSE477 L10 Inverter Dynamic View.4 Irwin&Vijay, PSU, 2001The Miller Effectq A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original valueVinCgd1M1Vout∆V∆VVinM1Vout∆V∆V2Cgb1CSE477 L10 Inverter Dynamic View.5 Irwin&Vijay, PSU, 2001Layout of Two Chained InvertersInOutMetal1VDDGND1.2 µm=2λ1.125/0.250.375/0.25PMOSNMOSPolysilicon2.3750.72.3750.71.125/0.25PMOS1.8750.31.8750.30.375/0.25NMOSPS (µm)AS (µm2)PD (µm)AD (µm2)W/L0.125 0.5CSE477 L10 Inverter Dynamic View.6 Irwin&Vijay, PSU, 2001C’s and Equivalent K’s (for 2.5 V inverter)low-to-highhigh-to-low0.70.590.860.79PMOS0.810.790.610.57NMOSKeqswKeqKeqswKeq6 fF/ µm20.22 fF/µm1.9 fF/ µm20.27 fF/ µmPMOS6 fF/ µm20.28 fF/µm2 fF/µm20.31 fF/ µmNMOSCoxCjswCjCoCSE477 L10 Inverter Dynamic View.7 Irwin&Vijay, PSU, 2001Review: Components of CL(0.25 micron)6.06.1∑CL0.120.12from extractionCw2.282.28(2 Cop)Wp+ CoxWpLpCG40.760.76(2 Con)Wn+ CoxWnLnCG31.151.5KeqpADpCj+ KeqswpPDpCjswCDB20.900.66KeqnADnCj+ KeqswnPDnCjswCDB10.610.612 Cop WpCGD20.230.232 Con WnCGD1Value (fF)L→HValue (fF)H→LExpressionC TermCSE477 L10 Inverter Dynamic View.8 Irwin&Vijay, PSU, 2001Inverter Propagation Delayq Propagation delay is proportional to the time-constant of the network formed by the pull-down resistor and the load capacitancetpHL= ln(2) ReqnCL= 0.69 ReqnCLtpLH= ln(2) ReqpCL= 0.69 ReqpCLtp= (tpHL+ tpLH)/2 = 0.69 CL(Reqn+ Reqp)/2q To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal.CSE477 L10 Inverter Dynamic View.9 Irwin&Vijay, PSU, 2001Inverter Transient Response-0.500.511.522.530 0.5 1 1.5 2 2.5VinVout (V)t (sec) x 10-10 VDD=2.5V0.25µmW/Ln= 1.5W/Lp= 4.5Reqn= 13 kΩReqp= 31 kΩCSE477 L10 Inverter Dynamic View.10 Irwin&Vijay, PSU, 2001Inverter Transient Response-0.500.511.522.530 0.5 1 1.5 2 2.5VinVout (V)t (sec) x 10-10 VDD=2.5V0.25µmW/Ln= 1.5W/Lp= 4.5Reqn= 13 kΩReqp= 31 kΩtpHL= 39.9 psec36 psectpLH= 31.7 psec29 psecsotp= 32.5 psectftrtpHLtpLHCSE477 L10 Inverter Dynamic View.11 Irwin&Vijay, PSU, 2001Inverter Propagation Delay, Revisitedq To see how a designer can optimize the delay of a gate have to expand the Reqin the delay equationtpHL= 0.69 ReqnCL= 0.69 (3/4 (CL VDD)/IDSATn)= 0.52 CL/ (W/Lnk’nVDSATn)11.522.533.544.555.50.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4VDD(V) tp(normalized)CSE477 L10 Inverter Dynamic View.12 Irwin&Vijay, PSU, 2001Design for Performanceq Reduce CLl internal diffusion capacitance of the gate itselfl interconnect capacitancel fanoutq Increase W/L ratio of the transistorl the most powerful and effective performance optimization tool in the hands of the designerl watch out for self-loading!q Increase VDDl only minimal improvement in performance at the cost of increased energy dissipationCSE477 L10 Inverter Dynamic View.13 Irwin&Vijay, PSU, 2001Device Sizing for Performanceq Divide capacitive load intol intrinsic - diffusion and Miller effectl extrinsic - wiring and fanoutCL= Cint+ Cext = Cint(1 + α)q Widening both PMOS and NMOS by a factor S reduces Reqby an identical factor, but raises the intrinsiccapacitance by the same factortp= (1 + α/S)tp0where tp0is the intrinsic delay of the gate (α = 0)CSE477 L10 Inverter Dynamic View.14 Irwin&Vijay, PSU, 2001Sizing Impacts on Delay22.22.42.62.833.23.43.63.81 3 5 7 9 11 13 15S tp(sec)x 10-11 Any sizing factor that is sufficiently larger than αwill give only minimal performance gains at substantial area costs.CSE477 L10 Inverter Dynamic View.15 Irwin&Vijay, PSU, 2001Impact of Fanoutq Extrinsic capacitance is a function of the fanout of the gate - the larger the fanout, the larger the external load. With fanout Ntp(N) = tp0 (1 + αN)q Linear dependencel avoid large fanout if performance is an issueq Increasing the sizing factor S of the driving inverter is recommended for larger fanoutCSE477 L10 Inverter Dynamic View.16 Irwin&Vijay, PSU, 2001NMOS/PMOS Ratioq So far have sized the PMOS and NMOS so that the Req’s match (ratio of 3 to 3.5)l symmetrical VTCl equal high-to-low and low-to-high propagation delaysq If speed is the only concern, reduce the width of the PMOS device!l widening the PMOS degrades the tpHL due to larger parasitic capacitanceβ = (W/Lp)/(W/Ln)r = Reqp/Reqn (resistance ratio of identically-sized PMOS and NMOS)βopt = √r when wiring capacitance is negligibleCSE477 L10 Inverter Dynamic View.17 Irwin&Vijay, PSU, 2001PMOS/NMOS Ratio Effects33.544.551 2 3 4 5βtp(sec)x 10-11 β of 2.4 (= 31 kΩ/ 13 kΩ) gives symmetrical responseβ of 1.6 to 1.9 gives optimal performancetpLHtptpHLCSE477 L10 Inverter Dynamic View.18 Irwin&Vijay, PSU, 2001Input Signal Rise/Fall Timeq In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging CLand impacts propagation delay.q tpincreases linearly with increasing input slope once ts> tpq Performance is affected by fanout and the driving strength of the gate(s) feeding its input.3.63.844.24.44.64.855.25.40 2 4 6 8ts(sec)tp(sec)x 10-11 x 10-11 for a minimum-size inverter with a fan-out of a single gateCSE477 L10 Inverter Dynamic View.19 Irwin&Vijay, PSU, 2001Design Challengeq Keep signal rise times smaller than or equal to the gate propagation delays.l good for performancel good for power consumptionq Keeping rise and fall times of the signals small and of approximately equal values is one of the major challenges in high-performance designs - slope engineering.CSE477 L10 Inverter Dynamic View.20 Irwin&Vijay, PSU, 2001Delay with Long Interconnectsq When gates are farther apart, wire capacitance and resistance can no longer be ignored.tp= 0.69RdrCint + (0.69Rdr+0.38Rw)Cw+ 0.69(Rdr+Rw)Cfan= 0.69Rdr(Cint+Cfan) + 0.69(Rdrcw+rwCfan)L + 0.38rwcwL2cintVoutcfan(rw, cw, L)CSE477 L10